# US 11,114,314 B2 · Method for fabrication of a semiconductor structure including an interposer free from any through via

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- Number: US 11,114,314 B2
- Document ID: US11114314B2
- Status: Granted
- Kind: B2
- Application number: 16/305,695
- Filed: 2017-05-24
- Published: 2020-10-15
- Granted: 2021-09-07
- Earliest claimed: 2016-05-30
- Assignees: Soitec
- Applicants: Soitec
- Inventors: Bich-Yen Nguyen; Ludovic Ecarnot; Nadia Ben Mohamed; Christophe Malville
- Web page: https://patentgrep.com/patent/US11114314B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 74/014: {using batch processing}
- H10W 74/114: {by a substrate and the encapsulations}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10P 72/7412: {the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support}
- H10P 72/7426: {used as a support during build up manufacturing of active devices}
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/7438: {with parts of the auxiliary support remaining in the finished device}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/66: Conductive materials thereof
- H10W 70/685: comprising multiple insulating layers
- H10W 72/01255: {by using masks}
- H10W 72/01257: {by reflowing}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/344: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 80/211: {using auxiliary members, e.g. aids for protecting the bonding area}
- H10W 80/301: {Bonding techniques, e.g. hybrid bonding}
- H10W 90/00: Package configurations
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/792: {between multiple chips}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor structure includes introducing, at selected conditions, hydrogen and helium species (e.g., ions) in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support; forming on the temporary support an interconnection layer; placing at least one semiconductor chip on the interconnection layer; assembling a stiffener on a back side of the at least one semiconductor chip; and providing thermal energy to the temporary support to detach the residual part and provide the semiconductor structure. The interconnection layer forms an interposer free from any through via.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
introducing, at selected conditions, hydrogen and helium species in a temporary support to form a plane of weakness at a predetermined depth therein, and to define a superficial layer and a residual part of the temporary support;
forming an interconnection layer on the temporary support, the interconnection layer comprising contact pads separated by a dielectric material and electrically conductive paths between the contact pads connecting the contact pads through the dielectric material;
placing at least one semiconductor chip on the interconnection layer to electrically couple conductive features of the chip with contact pads of the interconnection layer;
assembling a stiffener on a back side of the at least one semiconductor chip; and
providing energy to the temporary support to detach the residual part and provide the semiconductor structure.

### Claim 2 (depends on 1)

The method of claim 1, wherein the selected conditions of introduction of the helium species comprises implanting helium ions at a dose of between 1×1016 at/cm3 and 2×1016 at/cm3, and at an implantation energy of between 40 keV and 200 keV.

### Claim 3 (depends on 1)

The method of claim 1, wherein the selected conditions of introduction of the hydrogen species comprises implanting hydrogen ions at a dose of from 0.5×1016 at/cm3 to 1.5×1016 at/cm3, and at an implantation energy of between 25 keV and 200 keV.

### Claim 4 (depends on 1)

The method of claim 1, wherein the interconnection layer has a first surface on the side of the semiconductor chip and a second surface opposite the first surface, and wherein the contact pads are disposed on both the first surface and the second surface.

### Claim 5 (depends on 4)

The method of claim 4, further comprising at least partially removing the superficial layer after the detachment of the residual part to expose at least some contact pads on the second surface of the interconnection layer.

### Claim 6 (depends on 4)

The method of claim 4, further comprising forming an emerging feature on the contact pads on the first surface to facilitate the electrical coupling of conductive features of the semiconductor chip with the contact pads.

### Claim 7 (depends on 1)

The method of claim 1, further comprising forming elementary devices on and/or in the superficial layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein the superficial layer has a thickness less than about 10 micrometers.

### Claim 9 (depends on 1)

The method of claim 1, wherein a distance separating two juxtaposed contact pads is between 0.2 micrometer and 2 micrometers.

### Claim 10 (depends on 1)

The method of claim 1, wherein the assembling of the stiffener on the back side of the at least one semiconductor chip is performed after the placing of the at least one semiconductor chip on the interconnection layer.

### Claim 11 (depends on 1)

The method of claim 1, wherein the assembling of the stiffener on the back side of the at least one semiconductor chip is performed before the placing of the at least one semiconductor chip on the interconnection layer.

### Claim 12 (depends on 10, 11)

The method of any one of claim 10 or claim 11, wherein the assembling of the stiffener on the back side of the at least one semiconductor chip further comprises providing a filling material in a free space surrounding the at least one semiconductor chip.

### Claim 13 (depends on 1)

The method of claim 1, further comprising dicing the semiconductor structure to provide at least one raw semiconductor device, and packaging the at least one raw semiconductor device to form a final semiconductor device.

### Claim 14 (depends on 1)

The method of claim 1, wherein the interconnection layer has a thickness of between 200 nm and 20 micrometers.

### Claim 15 (depends on 1)

The method of claim 1, wherein a thermal budget associated with the formation of the interconnection layer is less than 250° C. for 4 hours or is less than 20 minutes at 350° C.

### Claim 16 (depends on 1)

The method of claim 1, wherein providing energy to the temporary support comprises applying thermal energy to the temporary support by applying a temperature of between 200° C. and 450° C. for a period of between 10 minutes and 2 hours.

### Claim 17 (depends on 1)

The method of claim 1, wherein providing energy to the temporary support comprises providing thermal energy and/or mechanical energy to the temporary support.

### Claim 18 (depends on 8)

The method of claim 8, wherein the superficial layer has a thickness of between 50 nm and 600 nm.