# US 11,114,311 B2 · Chip package structure and method for forming the same

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- Number: US 11,114,311 B2
- Document ID: US11114311B2
- Status: Granted
- Kind: B2
- Application number: 16/242,311
- Filed: 2019-01-08
- Published: 2020-03-05
- Granted: 2021-09-07
- Earliest claimed: 2018-08-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Po-Hao Tsai; Shih-Ting Hung; Shin-Puu Jeng; Techi Wong
- Web page: https://patentgrep.com/patent/US11114311B2

## CPC

- H10W 74/016: {using moulds}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/90: Bond pads, in general
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a chip package structure is provided. The method includes forming a conductive structure over a substrate. The substrate includes a dielectric layer and a wiring layer in the dielectric layer, and the conductive structure is electrically connected to the wiring layer. The method includes forming a first molding layer over the substrate and surrounding the conductive structure. The method includes forming a redistribution structure over the first molding layer and the conductive structure. The method includes bonding a chip structure to the redistribution structure.

## Claims

### Claim 1

A method for forming a chip package structure, comprising:
forming a wiring layer in a dielectric layer, wherein the dielectric layer is made of polymer;
forming a conductive structure over the dielectric layer, wherein the conductive structure is electrically connected to the wiring layer;
forming a first molding layer over the dielectric layer and surrounding the conductive structure and the dielectric layer, wherein a bottom surface of the dielectric layer and a bottom surface of the first molding layer face an identical direction;
forming a redistribution structure over the first molding layer and the conductive structure; and
bonding a chip structure to the redistribution structure to form the chip package structure, wherein the bottom surface of the dielectric layer and the bottom surface of the first molding layer are exposed from the chip package structure.

### Claim 2 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the first molding layer continuously covers a surface and a sidewall of the dielectric layer, the surface faces the redistribution structure, and the sidewall is adjacent to and surrounds the surface.

### Claim 3 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, further comprising:
forming a conductive bump over the dielectric layer after bonding the chip structure to the redistribution structure, wherein the dielectric layer is between the conductive bump and the redistribution structure.

### Claim 4 (depends on 3)

The method for forming the chip package structure as claimed in claim 3, further comprising:
cutting through the first molding layer and the redistribution structure after forming the conductive bump over the dielectric layer.

### Claim 5 (depends on 4)

The method for forming the chip package structure as claimed in claim 4, wherein a first sidewall of the first molding layer and a second sidewall of the redistribution structure are coplanar after cutting through the first molding layer and the redistribution structure.

### Claim 6 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the conductive structure passes through the first molding layer.

### Claim 7 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the redistribution structure is in direct contact with the conductive structure and the first molding layer.

### Claim 8 (depends on 1)

The method for forming the chip package structure as claimed in claim 1, wherein the chip structure is electrically connected to the dielectric layer through the redistribution structure and the conductive structure.

### Claim 9

A method for forming a chip package structure, comprising:
forming a wiring layer in a dielectric layer, wherein the dielectric layer is made of polymer;
forming a conductive structure over the dielectric layer, wherein the conductive structure is electrically connected to the wiring layer;
forming a first molding layer over the dielectric layer to surround the conductive structure;
removing the first molding layer over the conductive structure;
forming a redistribution structure over the first molding layer and the conductive structure, wherein the redistribution structure is in direct contact with the conductive structure;
bonding a chip structure to the redistribution structure,
removing a portion of the dielectric layer to form openings after bonding the chip structure; and
forming bumps in the openings of the dielectric layer.

### Claim 10 (depends on 9)

The method for forming the chip package structure as claimed in claim 9, wherein the forming of the conductive structure comprises:
forming a seed layer over the dielectric layer;
forming a mask layer over the seed layer, wherein the mask layer has an opening partially exposing the seed layer;
forming a conductive layer in the opening; and
removing the mask layer and the seed layer under the mask layer, wherein the conductive layer and the seed layer under the conductive layer together form the conductive structure.

### Claim 11 (depends on 9)

The method for forming the chip package structure as claimed in claim 9, wherein a first top surface of the first molding layer and a second top surface of the conductive structure are coplanar after removing the first molding layer over the conductive structure.

### Claim 12 (depends on 11)

The method for forming the chip package structure as claimed in claim 11, wherein the forming of the redistribution structure over the first molding layer and the conductive structure comprises:
forming the dielectric layer over the first molding layer and the conductive structure, wherein the dielectric layer has an opening exposing the conductive structure; and
forming the wiring layer over the dielectric layer and in the opening to connect to the conductive structure, wherein the chip structure is electrically connected to the wiring layer.

### Claim 13

A method for forming a chip package structure, comprising:
forming a wiring layer in a dielectric layer, wherein the dielectric layer is made of polymer;
forming a conductive structure over a top surface of the dielectric layer, wherein the conductive structure is electrically connected to the wiring layer;
forming a molding layer over the dielectric layer, wherein the conductive structure is exposed from the first molding layer;
forming a redistribution structure over the molding layer and the conductive structure, wherein the conductive structure is electrically connected to the redistribution structure;
bonding a chip structure to the redistribution structure; and
forming a bump in direct contact with a bottom surface of the dielectric layer to form the chip package structure, wherein the bump is exposed from the chip package structure.

### Claim 14 (depends on 13)

The method for forming the chip package structure as claimed in claim 13, further comprising forming an underfill layer partially covering the sidewall of the chip structure, wherein the molding layer partially covers the sidewall of the chip structure.

### Claim 15 (depends on 14)

The method for forming the chip package structure as claimed in claim 14, wherein the chip structure comprises a first chip and a second chip, the method further comprises removing a portion of the molding layer to expose a top surface of the first chip, and a top surface of the second chip is covered by the molding layer.

### Claim 16 (depends on 13)

The method for forming the chip package structure as claimed in claim 13, further comprises forming conductive bumps between the chip structure and the redistribution structure, wherein the chip structure comprises a first chip and a second chip, the conductive bumps comprises a first conductive bump between the first chip and the redistribution structure and a second conductive bump between the second chip and the redistribution structure, and the width of the first conductive bump and the second conductive bump are different.

### Claim 17 (depends on 13)

The method for forming the chip package structure as claimed in claim 13, wherein a first sidewall of the molding layer and a second sidewall of the redistribution structure are coplanar.

### Claim 18 (depends on 3)

The method for forming the chip package structure as claimed in claim 3, wherein the conductive bump is in direct contact with the wiring layer in the dielectric layer.

### Claim 19 (depends on 3)

The method for forming the chip package structure as claimed in claim 3, wherein the bump overlaps a portion of the dielectric layer in a tangent direction of the dielectric layer.

### Claim 20 (depends on 9)

The method for forming the chip package structure as claimed in claim 9, wherein the bumps are in direct contact with a bottom surface of the dielectric layer and exposed from the chip package structure.