Embedded packaging method capable of realizing heat dissipation

An embedded packaging method capable of realizing heat dissipation, comprising following steps of:

• S1:
• providing a frame having at least one through hole, the frame being vertically provided with a certain number of first copper pillars, and a lower surface of the frame being a first surface;
• S2:
• attaching a tape on the first surface so that an adhesive surface of the tape is attached to the first surface, and placing a device in the through hole with a contact of the device being attached to the tape;
• S3:
• completely filling the through hole with photosensitive insulating material and covering a second surface opposite to the first surface, exposing the first surface and the second surface with different energies, completely curing the photosensitive insulating material in a lower portion of the through hole while not completely curing the photosensitive insulating material in an upper portion of the through hole and covered on the second surface, exposing an upper surface of the device and at least part of a side surface of the device by developing, and forming holes in regions, corresponding to the first copper pillars, of the photosensitive insulating material covered on the second surface;
• S4:
• removing the tape, electroplating on the first surface to form a first metal layer, and electroplating on the upper surface and side surface of the device, an upper surface of the photosensitive insulating material and an upper end face of each of the first copper pillars to form a second metal layer, the second metal layer covering the upper end face of each of the first copper pillars and the upper surface and at least part of the side surface of the device;
• and
• S5:
• etching the first metal layer and the second metal layer to obtain a first circuit layer and a second circuit layer, respectively, the contact of the device being electrically connected to the first circuit layer, and an upper end and a lower end of each of the first copper pillars being electrically connected to the second circuit layer and the first circuit layer, respectively.