# US 11,114,301 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 11,114,301 B2
- Document ID: US11114301B2
- Status: Granted
- Kind: B2
- Application number: 16/984,033
- Filed: 2020-08-03
- Published: 2020-11-19
- Granted: 2021-09-07
- Earliest claimed: 2017-11-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.; National Taiwan University
- Inventors: Ming-Hwei Hong; Juei-Nai Kwo; Yen-Hsun Lin; Keng-Yung Lin; Bo-Yu Yang; Hsien-Wen Wan
- Web page: https://patentgrep.com/patent/US11114301B2

## CPC

- H10D 64/01358: {the insulator being formed after the semiconductor body, the semiconductor being a Group III-V material}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/027: {of lateral single-gate IGFETs}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 48/383: {Quantum effect devices, e.g. of devices using quantum reflection, diffraction or interference effects}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10P 14/6516: {of treatments performed after formation of the materials}
- H10P 14/6529: {by exposure to a gas or vapour}
- H10P 14/662: {Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548)}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69395: {the material containing zirconium, e.g. ZrO2}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/80: characterised by the materials
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/21: {of electrically active species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate, a gate structure, and source/drain regions. The gate structure comprises an yttrium oxide layer over the semiconductor substrate, an aluminum oxide layer over the yttrium oxide layer, and a gate electrode on the aluminum oxide layer. The source/drain regions are on the semiconductor substrate and on opposite sides of the gate structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor substrate;
a gate structure comprising:
an yttrium oxide layer over the semiconductor substrate;
an aluminum oxide layer over the yttrium oxide layer;
a first high-k dielectric layer over the aluminum oxide layer, wherein the first high-k dielectric layer is made of a material different than the aluminum oxide layer and the yttrium oxide layer; and
a gate electrode on the first high-k dielectric layer; and
source/drain regions on the semiconductor substrate and on opposite sides of the gate structure.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the yttrium oxide layer is in contact with the aluminum oxide layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the yttrium oxide layer is in contact with the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the aluminum oxide layer has a thickness greater than the yttrium oxide layer.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor substrate comprises gallium arsenic.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor substrate has a (001) surface orientation.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the first high-k dielectric layer is made of at least one of hafnium oxide or lanthanum oxide.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first high-k dielectric layer is in direct contact with the aluminum oxide layer.

### Claim 9

A semiconductor device, comprising:
a substrate;
a semiconductor fin extending upwardly from the substrate;
a first high-k dielectric layer extending across the semiconductor fin;
a second high-k dielectric layer over the first high-k dielectric layer and having a material different from the first high-k dielectric layer;
a third high-k dielectric layer over the second high-k dielectric layer and having a material different from the second high-k dielectric layer, wherein the material of the third high-k dielectric layer is the same as the first high-k dielectric layer;
a gate electrode on the third high-k dielectric layer; and
source/drain regions on the semiconductor fin and on opposite sides of the gate electrode.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the first high-k dielectric layer is aluminum-free.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein a dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the second high-k dielectric layer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein a dielectric constant of the second high-k dielectric layer is less than a dielectric constant of the third high-k dielectric layer.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, further comprising a fourth high-k dielectric layer over the third high-k dielectric layer, wherein the fourth high-k dielectric layer has a material different than the third high-k dielectric layer.

### Claim 14 (depends on 9)

The semiconductor device of claim 9, wherein the first high-k dielectric layer has a thickness less than about 5 Å.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein the first high-k dielectric layer is made of yttrium oxide.

### Claim 16 (depends on 9)

The semiconductor device of claim 9, wherein the second high-k dielectric layer is made of aluminum oxide.

### Claim 17

A method for manufacturing a semiconductor device, the method comprising:
forming a first high-k dielectric layer over a semiconductor substrate;
forming a second high-k dielectric layer over the first high-k dielectric layer and having a material different from the first high-k dielectric layer;
implanting the semiconductor substrate with a dopant through the first and second high-k dielectric layers to form source/drain regions;
after implanting the semiconductor substrate, patterning the first and second high-k dielectric layers to expose the source/drain regions; and
forming a gate electrode over the second high-k dielectric layer and laterally between the source/drain regions, wherein patterning the first and second high-k dielectric layers is performed such that a first remainder of the first and second high-k dielectric layers is below the gate electrode and extends past a first side of one of the source/drain regions and a second remainder of the first and second high-k dielectric layers extends past a second side of the one of the source/drain regions opposite the first side of the one of the source/drain regions, and the second remainder of the first and second high-k dielectric layers non-overlaps with the gate electrode.

### Claim 18 (depends on 17)

The method of claim 17, wherein forming the gate electrode over the second high-k dielectric layer is performed prior to implanting the semiconductor substrate with the dopant.

### Claim 19 (depends on 17)

The method of claim 17, wherein forming the gate electrode over the second high-k dielectric layer is performed prior to patterning the first and second high-k dielectric layers.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
forming a third high-k dielectric layer over the second high-k dielectric layer and made of a material the same as the first high-k dielectric layer and different than the second high-k dielectric layer.