# US 11,114,296 B2 · Semiconductor wafer, electronic device, method of performing inspection on semiconductor wafer, and method of manufacturing electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,296 B2 - Document ID: US11114296B2 - Status: Granted - Kind: B2 - Application number: 16/549,906 - Filed: 2019-08-23 - Published: 2019-12-19 - Granted: 2021-09-07 - Earliest claimed: 2017-02-26 - Assignees: Sumitomo Chemical Company, Limited - Applicants: Sumitomo Chemical Company, Limited - Inventors: Noboru Fukuhara; Yasuyuki Kurita; Takayuki Inoue - Web page: https://patentgrep.com/patent/US11114296B2 ## CPC - H10P 14/3458: {Monocrystalline} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10D 62/357: {of FETs} - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10D 64/514: {characterised by the insulating layers} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G01R 31/2644: {Adaptations of individual semiconductor devices to facilitate the testing thereof} - H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed. ## Claims ### Claim 1 A semiconductor wafer comprising: a substrate; a buffer layer; a first crystalline layer; and a second layer, wherein the substrate, the buffer layer, the first crystalline layer, and the second layer are positioned in order of the substrate, the buffer layer, the first crystalline layer and the second layer, the buffer layer and the first crystalline layer are made of a group III nitride layer, a bandgap of the first crystalline layer is smaller than a bandgap of the second layer, when the semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer, and with a first electrode and a second electrode, electrically connected to the channel, provided closer to a front surface than the channel is, and with a third electrode, at which an electric field is applicable to a spatial region positioned between the channel and the substrate, provided closer to a back surface than the channel is, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed. ### Claim 2 A semiconductor wafer comprising: a substrate; a buffer layer; a first crystalline layer; and a second layer, wherein the substrate, the buffer layer, the first crystalline layer, and the second layer are positioned in order of the substrate, the buffer layer, the first crystalline layer, and the second layer, the buffer layer and the first crystalline layer are made of a group III nitride layer, a bandgap of the first crystalline layer is smaller than a bandgap of the second layer, when the semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer, and with a first electrode and a second electrode, electrically connected to the channel, provided closer to a front surface than the channel is, when voltage at a level not causing saturation of current flowing between the first electrode and the second electrode is applied between the first electrode and the second electrode and negative voltage is applied to the wafer with a lower one of potentials of the first electrode and the second electrode serving as a reference, the current flowing between the first electrode and the second electrode does not decrease with time. ### Claim 3 (depends on 1) The semiconductor wafer according to claim 1, wherein the second layer is a second crystalline layer made of a group III nitride layer, and the channel is two-dimensional electron gas. ### Claim 4 (depends on 3) The semiconductor wafer according to claim 3, wherein the first crystalline layer is made of AlxGa1-xN and the second crystalline layer is made of AlyGa1-yN where x≠y. ### Claim 5 (depends on 4) The semiconductor wafer according to claim 4, wherein the wafer is made of a conductive monocrystalline Si, the first crystalline layer is made of GaN, and the second crystalline layer is made of AlyGa1-yN where 0