# US 11,114,176 B1 · Systems and methods to provide write termination for one time programmable memory cells

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- Number: US 11,114,176 B1
- Document ID: US11114176B1
- Status: Granted
- Kind: B1
- Application number: 16/811,145
- Filed: 2020-03-06
- Published: 2021-09-09
- Granted: 2021-09-07
- Earliest claimed: 2020-03-06
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Hochul Lee; Anil Chowdary Kota; Keejong Kim
- Web page: https://patentgrep.com/patent/US11114176B1

## CPC

- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- G11C 7/227: {Timing of memory operations based on dummy memory elements or replica circuits}
- G11C 17/16: using electrically-fusible links
- G11C 16/3481: {Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming}
- G11C 16/3486: {Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming}
- G11C 17/14: in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
- G11C 29/027: {in fuses}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

## Claims

### Claim 1

A One Time Programmable (OTP) memory, comprising:
a first driver coupled to a reference cell by a first bit line;
a second driver coupled to an OTP cell by a second bit line; and
a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

### Claim 2 (depends on 1)

The OTP memory of claim 1, wherein the OTP cell comprises an electronic fuse (e-fuse).

### Claim 3 (depends on 1)

The OTP memory of claim 1, wherein the OTP cell comprises an antifuse.

### Claim 4 (depends on 1)

The OTP memory of claim 1, wherein the comparator comprises a symmetrical sense amplifier.

### Claim 5 (depends on 1)

The OTP memory of claim 1, wherein the logic circuit comprises an OR gate having a first input configured to receive an enable signal and a second input configured to receive an output signal from the comparator.

### Claim 6 (depends on 1)

The OTP memory of claim 1, wherein the reference cell comprises a resistor between the first bit line and a word line transistor, wherein the resistor is sized to cause a reference voltage at the first bit line that is lower than a voltage at the second bit line associated with the OTP cell being blown.

### Claim 7 (depends on 1)

The OTP memory of claim 1, wherein the reference cell comprises a resistor between the first bit line and a word line transistor, wherein the resistor is sized to cause a reference voltage at the first bit line that is greater than a voltage at the second bit line associated with the OTP cell being unblown.

### Claim 8 (depends on 1)

The OTP memory of claim 1, wherein the OTP cell comprises a fuse between the second bit line and a word line transistor.

### Claim 9 (depends on 1)

The OTP memory of claim 1, wherein the first input of the comparator is coupled to the first bit line by a read word line transistor.

### Claim 10 (depends on 1)

The OTP memory of claim 1, wherein the second input of the comparator is coupled to the second bit line by a read word line transistor.

### Claim 11 (depends on 1)

The OTP memory of claim 1, wherein the first bit line comprises a read bit line.

### Claim 12 (depends on 1)

The OTP memory of claim 1, wherein the second bit line comprises a read bit line.

### Claim 13 (depends on 1)

The OTP memory of claim 1, further comprising:
wherein the logic circuit comprises a multiplexor coupled to a third driver having an additional OTP cell, and wherein the multiplexor is configured to provide an enable signal to the second driver and to the third driver.

### Claim 14

A method comprising:
applying a driver control signal to a first driver coupled to a reference cell by a first bit line;
applying the driver control signal to a second driver coupled to an OTP cell by a second bit line;
generating a first current by the first driver, thereby generating a reference voltage at a first input of a comparator that is coupled to the first bit line;
generating a second current by the second driver, thereby generating an OTP cell voltage at a second input of the comparator that is coupled to the second bit line;
adjusting the driver control signal in response to a change of the OTP cell voltage associated with the OTP cell being blown by the second current;
changing an output signal of the comparator; and
adjusting the driver control signal based on the output signal of the comparator.

### Claim 15 (depends on 14)

The method of claim 14, wherein adjusting the driver control signal comprises de-asserting a driver enable signal to the first driver and to the second driver.

### Claim 16 (depends on 14)

The method of claim 14, wherein adjusting the driver control signal comprises asserting a driver enable signal to the first driver and to the second driver.

### Claim 17 (depends on 14)

The method of claim 14, wherein adjusting the driver control signal comprises causing the second driver to stop generating the second current.

### Claim 18 (depends on 14)

The method of claim 14, wherein generating the second current comprises:
blowing a fuse of the OTP cell.

### Claim 19 (depends on 14)

The method of claim 14, wherein generating the second current comprises:
blowing an antifuse of the OTP cell.

### Claim 20

A Read Only Memory (ROM), comprising:
means for producing a first current on a first bit line;
means for producing a second current on a second bit line;
a reference resistor coupled between the first bit line and a ground;
a One Time Programmable (OTP) cell coupled between the second bit line and the ground; and
means for turning off the second current producing means in response to a change in a voltage at the second bit line relative to a voltage at the first bit line.

### Claim 21 (depends on 20)

The ROM of claim 20, wherein the turning off means comprises a comparator having a first input coupled to the first bit line, a second input coupled to the second bit line, and an output coupled to a logic circuit configured to enable the first current producing means and the second current producing means.

### Claim 22 (depends on 20)

The ROM of claim 20, further comprising a multiplexor coupled to the second current producing means and a means for producing a third current on a third bit line.

### Claim 23 (depends on 22)

The ROM of claim 22, further comprising a control circuit configured to provide an N-bit input to the multiplexor, wherein Nis an integer equal to a number of OTP cells in the ROM.

### Claim 24 (depends on 20)

The ROM of claim 20, wherein the turning off means comprises a sense amplifier configured to receive the voltage at the second bit line and the voltage at the first bit line.

### Claim 25 (depends on 20)

The ROM of claim 20, wherein the OTP cell comprises an antifuse.

### Claim 26 (depends on 20)

The ROM of claim 20, wherein the first current producing means comprises an inverter coupled to the first bit line, the inverter configured to receive an enable signal from the turning off means.

### Claim 27 (depends on 20)

The ROM of claim 20, wherein the turning off means comprises:
a comparator configured to receive the voltage of the first bit line and the voltage at the second bit line; and
an OR gate receiving an output of the comparator and configured to provide an enable signal to the first current producing means and the second current producing means.

### Claim 28 (depends on 20)

The ROM of claim 20, wherein the reference resistor is sized to cause the voltage at the first bit line to be lower than the voltage at the second bit line when the OTP cell is blown.

### Claim 29 (depends on 20)

The ROM of claim 20, wherein the reference resistor is sized to cause the voltage at the first bit line to be higher than the voltage at the second bit line when the OTP cell is unblown.

### Claim 30 (depends on 20)

The ROM of claim 20, wherein a first input of the turning off means is coupled to the first bit line by a read word line transistor.