Systems and methods for providing a read only memory cell array

A Read Only Memory (ROM) cell array comprising:

• a first transistor coupled to a first word line;
• a second transistor coupled to a second word line;
• a third transistor disposed between the first transistor and the second transistor, the third transistor having a first gate terminal permanently coupled to a power rail
• a first bit line, a second bit line, and a first source line;
• and
• a first logic gate and a second logic gate, the first logic gate coupled to the first source line and the first bit line and configured to output a first bit stored by the first transistor, the second logic gate coupled to the first source line and the second bit line and configured to output a second bit stored by the first transistor.

A method of reading a read-only memory (ROM) cell array having a first transistor corresponding to a first word line and a second transistor corresponding to a second word line, the method comprising:

• applying a first signal on the first word line to read data stored to the first transistor;
• applying a second signal on the second word line to read data stored to the second transistor;
• and
• maintaining a third transistor in an off state during reading the data stored to the first transistor and during reading the data stored to the second transistor, wherein the third transistor is disposed in series between the first transistor and the second transistor;
• wherein the ROM cell is further arranged to have a fourth transistor coupled to a third word line, the fourth transistor being coupled to the second transistor on a side opposite the third transistor, and a fifth transistor coupled to the fourth transistor and having a second gate terminal permanently coupled to a power rail.

A system on chip (SOC) having a read only memory (ROM) unit, the ROM unit comprising:

• a first group of transistors, each storing data and coupled to a first group of word lines;
• a second group of transistors, each storing data and coupled to a second group of word lines;
• and
• a dummy word line transistor isolating the first group of transistors from the second group of transistors, the dummy word line transistor being permanently in an off state, wherein a first transistor within the first group of transistors is associated with a first bit line, a second bit line, and a first source line and configured to store two binary bits, and wherein a second transistor within the second group of transistors is associated with a third bit line, fourth bit line, and a second source line and configured to store two binary bits.

A read only memory (ROM) cell array comprising:

• first means for storing first data, the first means associated with a first word line and a first bit line;
• second means for storing second data, the second means associated with a second word line and a second bit line;
• and
• means for isolating the first means from the second means, the isolating means being arranged between the first means and the second means on a semiconductor substrate, the first means, the second means, and the isolating means being arranged along a length dimension of the first bit line and the second bit line, the isolating means including a transistor configured to be held permanently in an off state during operation of a chip on which the ROM cell array is implemented;
• third means for storing third data, the third means associated with a third word line, the third means being coupled to the second means on a side opposite the isolating means;
• and
• an additional isolating means for isolating the third means, the additional isolating means being coupled to the third means and having a gate terminal permanently coupled to a power rail.