Non-volatile memory device

A non-volatile memory device, comprising:

• a first chip including a memory cell region, the memory cell region including a first metal pad exposed at a lower surface of the first chip, and a memory cell array including a plurality of memory cells;
• and
• a second chip combined with the first chip in a stack and including a peripheral circuit region, the peripheral circuit region including a second metal pad exposed at an upper surface of the second chip, an output driver configured to output a data signal, and an operating signal generator configured to generate a plurality of operating signals for operating the output driver, and vertically connected to the memory cell region by bonding the first metal pad and the second metal pad together;
• wherein the output driver includes:
• a pull-up driver including a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors;
• and
• a pull-down driver having a plurality of N-type transistors, wherein one or more power supply voltages having different voltage levels are configured to be selectively applied to the pull-up driver.

A non-volatile memory device, comprising:

• a first chip including a memory cell region, the memory cell region including a first metal pad exposed at a lower surface of the first chip, and a memory cell array including a plurality of memory cells;
• and
• a second chip combined with the first chip in a stack and including a peripheral circuit region, the peripheral circuit region including a second metal pad exposed at an upper surface of the second chip, an output driver configured to output a data signal, and an operating signal generator configured to generate a plurality of operating signals for operating the output driver, and vertically connected to the memory cell region by bonding the first metal pad and the second metal pad together;
• wherein the output driver includes:
• a pull-up driver including a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors;
• and
• a pull-down driver including a first pull-down driver having a plurality of P-type transistors and a second pull-down driver having a plurality of N-type transistors.