US 11,114,170 B2Granted

Memory system

AssigneeKioxia Corporation

InventorsTakaya Handa, Yoshihisa Kojima, Kiyotaka Iwasaki

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Abstract

A semiconductor memory device includes a memory cell array, an input/output circuit configured to output read data from the semiconductor memory device, a first data latch configured to latch data read from the memory cell array as the read data, a second data latch to which the read data is transferred from the first data latch and from which the read data is transferred to the input/output circuit, a signaling circuit configured to output a ready signal or a busy signal, and a control circuit configured to control the signaling circuit to output the busy signal while the read data is being latched in the first data latch during a read operation performed on the memory cell array and to output the ready signal while the read data latched in the first data latch is being transferred from the first latch to the second latch.

Claims20

Dependent claims

A semiconductor memory device comprising:

a memory cell array including a plurality of memory cells, each memory cell being capable of storing data;
a sense circuit configured to sense the data stored in a memory cell of the plurality of memory cells;
a first data latch configured to latch data sensed from the memory cell by the sense circuit;
a second data latch configured to receive the data from the first data latch;
a status register configured to store information indicating whether the semiconductor memory device is in a ready state or in a busy state;
an input/output circuit configured to output from the semiconductor memory device the data received from the second data latch and the information received from the status register;
and
a control circuit configured to control the status register to store the information indicating the busy state upon receipt of a read command and to control the status register to store the information indicating the ready state, before completion of transfer of the data sensed from the memory cell from the first data latch to the second data latch.

5 more elements

A method of controlling, by a control circuit, a read operation in a semiconductor memory device including a memory cell array that includes a plurality of memory cells each being capable of storing data, a sense circuit configured to sense the data stored in a memory cell of the plurality of the memory cells, a first data latch configured to latch data sensed from the memory cell by the sense circuit, a second data latch configured to receive the data from the first data latch, a status register configured to store information indicating whether the semiconductor memory device is in a ready state or in a busy state, and an input/output circuit configured to output from the semiconductor memory device the data received from the second data latch and the information received from the status register, said method comprising:

receiving a read command;
and
responsive to receiving the read command, controlling the status register to store the information indicating the busy state, and before completion of transfer of the data sensed from the memory cell from the first data latch to the second data latch, controlling the status register to store the information indicating the ready state.

Dependencies are inferred from the claim text.

Facts

Application: 16/886,546Filed 28 May 2020 · continuation
Priority: JP JP2017-25136727 Dec 2017
Published: US 2020/0294605 A117 Sep 2020
Granted: 7 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

G11C 16/26
Auxiliary circuits, e.g. for writing into memory: sensing or reading circuits; Data output circuits
G11C 7/106
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output latches
G11C 7/1063
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: control signal…
G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…

Family

Application16/115,516Parent of this continuation · filed 28 Aug 2018
US 2020/0294605 A1Pre-grant publication · published 17 Sep 2020
US 10,706,940 B2Parent of this continuation
US 2019/0198120 A1Published application
US 11,114,170 B2This patent

From the US filing history. Foreign family members aren’t listed.