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US 11,114,167 B2Granted
Page buffer and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsSe Won Yun, Kyung Min Kang, Dong Ku Kang
Life of this patent
Estimating the term…
Abstract
Systems and methods are described including a page buffer to reduce a threshold voltage distribution skew of memory cells and improve programming performance. The page buffer includes a first circuit element connected to a first terminal for supplying a first bitline voltage, a second circuit element connected to a second terminal for supplying a second bitline voltage, and a latch configured to control the first and second circuit elements.
Claims19
A page buffer configured to supply a bitline voltage to a bitline connected to a plurality of memory cells, the page buffer comprising:
- a first circuit element connected to a first terminal for supplying a first bitline voltage;
- a second circuit element connected to a second terminal for supplying a second bitline voltage lower than the first bitline voltage;
- and
- a latch configured to control the first and second circuit elements based on whether a selected memory cell is one of the plurality of memory cells, and to input one of the first and second bitline voltages to the bitline,
- wherein when the selected memory cell is one of the plurality of memory cells, a level of the second bitline voltage is lower than a level of the first bitline voltage and higher than or equal to a level of a ground voltage, based on information of a channel connected to the bitline, and
- wherein the first bitline voltage is supplied to a selected bitline, the second bitline voltage is supplied to an unselected bitline, and the second bitline voltage is determined based on a thickness of a gate insulating layer of the channel.
3 more elements
A memory device comprising:
- a plurality of bitlines comprising a first bitline and a second bitline;
- a memory cell array comprising a plurality of memory cell strings connected to the plurality of bitlines, the plurality of memory cell strings comprising a first memory cell string connected to the first bitline and comprising a plurality of first memory cells, and a second memory cell string connected to the second bitline and comprising a plurality of second memory cells;
- and
- a page buffer configured to input a first bitline voltage to the first bitline in a first program operation on at least one of the first memory cells and to input a second bitline voltage, different from the first bitline voltage, to the second bitline in a second program operation on at least one of the second memory cells,
- wherein a first gate insulating layer of the first memory cell string has a thickness smaller than a thickness of a second gate insulating layer of the second memory cell string, and the first bitline voltage is higher than the second bitline voltage.
2 more elements
A memory device comprising:
- a substrate;
- a plurality of wordlines stacked on a top surface of the substrate;
- a plurality of wordline cut regions dividing the plurality of wordlines into a plurality of regions and extending in a direction perpendicular to the top surface of the substrate;
- a first channel disposed at a first distance from a first wordline cut region among the plurality of wordline cut regions, in a first direction parallel to the top surface of the substrate;
- a second channel disposed at a second distance, smaller than the first distance, from the first wordline cut region in the first direction;
- and
- a controller configured to supply a first bitline voltage to a first bitline connected to the first channel in a program operation on a first memory cell connected to the first channel and to supply a second bitline voltage, higher than the first bitline voltage, to a second bitline connected to the second channel in a program operation on a second memory cell connected to the second channel.
4 more elements
Dependencies are inferred from the claim text.