US 11,114,166 B2Granted

Semiconductor memory device

AssigneeToshiba Memory Corporation

InventorsAtsushi Okuyama, Yoshihiko Kamata, Hiromitsu Komai, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Hiroyuki Kaga

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Abstract

According to one embodiment, a semiconductor memory device includes a bit line electrically connected to a memory cell, a first node electrically connected to the bit line, a first driver configured to increase a voltage of the first node to a first voltage, a first buffer circuit configured to store data based on the voltage of the first node, a bus electrically connected to the first buffer circuit, a first transistor electrically connected between the first node and the bus, and a second buffer circuit electrically connected to the bus. The first buffer circuit is electrically connected to an input terminal of the first driver. The first driver changes a voltage of the bus based on the data stored in the first buffer circuit.

Claims16

Dependent claims

A semiconductor memory device comprising:

a bit line electrically connected to a memory cell;
a first node electrically connected to the bit line;
a first driver configured to increase a voltage of the first node to a first voltage;
a first buffer circuit configured to store data based on the voltage of the first node;
a bus electrically connected to the first buffer circuit;
a first transistor electrically connected between the first node and the bus;
a second transistor electrically connected between the first buffer circuit and the bus;
and
a second buffer circuit electrically connected to the bus,
wherein:
the first buffer circuit includes a third transistor electrically connected to the second transistor;
the first buffer circuit is electrically connected to an input terminal of the first driver;
an output terminal of the first driver is electrically connected to a second node between the bit line and the first node;
the first driver changes a voltage of the bus based on the data stored in the first buffer circuit;
and
the voltage of the bus is decreased or increased by setting the first transistor and the second transistor to a conducting state.

13 more elements

A semiconductor memory device comprising:

a bit line electrically connected to a memory cell;
a first transistor electrically connected to the bit line;
a second transistor electrically connected to the first transistor via a first node;
a first driver electrically connected to the first node and configured to apply a first voltage to the bit line;
a third transistor electrically connected to the second transistor via a second node;
a bus electrically connected to the third transistor;
a fourth transistor including a gate electrically connected to the second node;
a first storage circuit including a first terminal and a second terminal, the first terminal being electrically connected to the fourth transistor;
a fifth transistor electrically connected between the first terminal of the first storage circuit and the bus;
and
a second storage circuit electrically connected to the bus, wherein:
the first storage circuit includes a sixth transistor electrically connected to the fifth transistor;
the second terminal of the first storage circuit is electrically connected to an input terminal of the first driver;
an output terminal of the first driver is electrically connected to the first node between the first transistor and the second transistor;
the first driver decreases or increases a voltage of the bus based on a voltage of the second terminal of the first storage circuit;
and
the voltage of the bus is decreased or increased by setting the third transistor and the fifth transistor to a conducting state.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/561,454Filed 5 Sep 2019
Priority: JP JP2018-24013121 Dec 2018
Published: US 2020/0202948 A125 Jun 2020
Granted: 7 Sep 2021
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/24
Auxiliary circuits, e.g. for writing into memory: bit-line control circuits
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits
G11C 11/5671
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge trapping in…
G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series