Semiconductor devices having increased efficiency in generation of gate-induced drain leakage current without insulation deterioration and methods of operating the same

A semiconductor device comprising:

• a plurality of bitlines;
• a common source line configured to receive an erasing voltage during an erasing operation;
• at least one memory cell string connected between one bit line of the plurality of bitlines and the common source line, the at least one memory cell string including a plurality of memory cells, and at least one string select line connected to the one bit line;
• a gate-induced drain leakage (GIDL) line electrically connected to the common source line, the GIDL line configured to receive a GIDL voltage, the received GIDL voltage being increased while maintaining a constant voltage difference with the erasing voltage until the erasing voltage reaches a target voltage during the erasing operation;
• a ground select line connected to the GIDL line;
• and
• a plurality of wordlines connected to the string select line and the ground select line;
• wherein an overshoot occurs to apply a voltage higher than the target voltage after the erasing voltage, applied to the common source line, reaches the target voltage during the erasing operation.

A semiconductor device comprising:

• a substrate;
• a source layer on an upper surface of the substrate;
• a plurality of gate electrode layers, the plurality of gate electrode layers includes a lowermost gate electrode configured to provide a gate-induced drain leakage (GIDL) line;
• a plurality of insulating layers, the plurality of insulating layers and the plurality of gate electrode layers stacked alternately on the source layer;
• a plurality of channel structures, each of the plurality of channel structures having a vertical insulating layer and a vertical channel layer, the plurality of channel structures extending in a first direction perpendicular to the upper surface of the substrate;
• a common source extension region including a portion of the source layer which extends along the vertical channel layer, the common source extension region formed to overlap at least a portion of the GIDL line;
• and
• a memory controller configured to provide a high magnitude voltage to the source layer during an erasing operation, the high magnitude voltage having a magnitude greater than a magnitude of an erasing voltage of the erasing operation.