# US 11,114,163 B2 · Memory device and method of operating the same

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- Number: US 11,114,163 B2
- Document ID: US11114163B2
- Status: Granted
- Kind: B2
- Application number: 16/891,561
- Filed: 2020-06-03
- Published: 2020-09-17
- Granted: 2021-09-07
- Earliest claimed: 2017-08-01
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Hee Joung Park; Kyeong Seung Kang; Won Chul Shin
- Web page: https://patentgrep.com/patent/US11114163B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 11/5671: {using charge trapping in an insulator}
- G11C 16/24: Bit-line control circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 2211/563: Multilevel memory reading aspects
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C 2211/5647: Multilevel memory with bit inversion arrangement
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Presented herein is a memory device and a method of operating the memory device. The memory device may include a memory cell, and a page buffer coupled to the memory cell via a bit line and configured to perform a read operation on the memory cell. The page buffer may include a storage unit configured to control a bit line precharge operation during the read operation and to store a result value of a first sensing operation. After the bit line precharge operation, a value stored in the storage unit is inverted before the storage unit stores the result value of the first sensing operation.

## Claims

### Claim 1

A method of operating a memory device, comprising:
a first sensing operation using a first read voltage, comprising:
changing a voltage of a sense node of a page buffer of the memory device based on whether a threshold voltage of a memory cell of the memory device is greater than the first read voltage;
floating the sense node;
resetting a storage unit of the page buffer while the sense node floats; and
controlling a value stored in the storage unit based on the voltage of the sense node;
a bit line recovery operation of controlling a voltage of a bit line coupled to the memory cell based on the value stored in the storage unit; and
a second sensing operation using a second read voltage greater than the first read voltage.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the bit line recovery operation comprises changing a voltage of a word line coupled to the memory cell.

### Claim 3 (depends on 2)

The method according to claim 2, wherein changing the voltage of the word line coupled to the memory cell comprises:
changing the voltage applied to the word line from the first read voltage to the second read voltage.

### Claim 4 (depends on 1)

The method according to claim 1, wherein, when the voltage of the sense node is at a low level, the bit line recovery operation comprises electrically connecting the bit line to a ground node.

### Claim 5 (depends on 1)

The method according to claim 1, wherein, when the voltage of the sense node is at a high level, the value stored in the storage unit is inverted.