Non-volatile semiconductor memory device including a first memory bunch and a second memory bunch

A semiconductor memory device comprising:

• a first memory bunch comprising:
• a first source line extending in a first direction and a second direction perpendicular to the first direction;
• a first source side selecting gate transistor arranged on one side in a third direction intersecting the first direction and the second direction of the first source line;
• a first source side selecting gate line connected to a gate of the first source side selecting gate transistor, the first source side selecting gate line extending in the first direction and the second direction;
• a plurality of first non-volatile memory cells series connected to the first source side selecting gate transistor, the plurality of first non-volatile memory cells arranged on the one side in the third direction of the first source side selecting gate transistor;
• a plurality of first word lines stacked in the third direction and each connected to a gate of a corresponding one of the plurality of first non-volatile memory cells, the plurality of first word lines extending in the first direction and the second direction;
• a first drain side selecting gate transistor connected to one of the plurality of first non-volatile memory cells, the first drain side selecting gate transistor arranged on the one side in the third direction of the plurality of first non-volatile memory cells;
• a first drain side selecting gate line connected to a gate of the first drain side selecting gate transistor, the first drain side selecting gate line extending in the first direction and the second direction;
• and
• a first bit line connected to the first drain side selecting gate transistor, the first bit line arranged on the one side in the third direction of the first drain side selecting gate line, a longitudinal direction of the first bit line being in the second direction;
• a second memory bunch comprising:
• a second source line extending in the first direction and the second direction, the second source line arranged on the one side in the third direction of the first bit line;
• a second source side selecting gate transistor arranged on the one side in the third direction of the second source line;
• a second source side selecting gate line connected to a gate of the second source side selecting gate transistor, the second source side selecting gate line extending in the first direction and the second direction;
• a plurality of second non-volatile memory cells series connected to the second source side selecting gate transistor, the plurality of second non-volatile memory cells arranged on the one side in the third direction of the second source side selecting gate transistor;
• a plurality of second word lines stacked in the third direction and each connected to a gate of a corresponding one of the plurality of second non-volatile memory cells, the plurality of second word lines extending in the first direction and the second direction and the plurality of second word lines overlapping with the plurality of first word lines in the third direction;
• a second drain side selecting gate transistor connected to one of the plurality of second non-volatile memory cells, the second drain side selecting gate transistor arranged on the one side in the third direction of the plurality of second non-volatile memory cells;
• a second drain side selecting gate line connected to a gate of the second drain side selecting gate transistor, the second drain side selecting gate line extending in the first direction and the second direction;
• and
• a second bit line connected to the second drain side selecting gate transistor, the second bit line arranged on the one side in the third direction of the second drain side selecting gate line, a longitudinal direction of the second bit line being in the second direction;
• a first vertical bit line connected to the first bit line, a longitudinal direction of the first vertical bit line being in the third direction;
• and
• a second vertical bit line connected to the second bit line, a longitudinal direction of the second vertical bit line being in the third direction,
• wherein a longitudinal direction of the first vertical bit line is along the third direction from at least a position corresponding to the second drain side selecting gate transistor to a position corresponding to the second source side selecting gate transistor in the third direction.