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US 11,114,155 B2Granted
High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read
AssigneeMarvell Asia Pte Ltd
InventorsIgor Arsovski, Akhilesh Patil, Eric D. Hunt-Schroeder
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Abstract
The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N−1 of the consecutive read operations, and N is an integer number of the consecutive read operations.
Claims20
A memory structure comprising:
- an array of storage cells comprising bit lines and N storage cells, wherein the N storage cells are accessible via a first word line, and where N is an integer greater than two;
- at least one of
- a single sense amplifier configured to sense bits from N−1 storage cells of the N storage cells during N−1 consecutive read operations, or
- a first latch configured to latch the bits from the N−1 storage cells during the N−1 consecutive read operations;
- and
- a read controller configured to, during the N−1 consecutive read operations, i) precharge the bit lines once, ii) access at least N−1 of the N storage cells via the first word line, and, iii) awhile holding the first word line active, signal at least one of the single sense amplifier or the first latch to acquire the bits of the N−1 storage cells.
3 more elements
A method of reading from a memory structure, the method comprising:
- performing N−1 consecutive read operations including sensing bits from N storage cells along a first word line of the memory structure, where N is an integer greater than two, and wherein, during the N−1 consecutive read operations, the bit of the N−1th storage cell and the bit of the Nth storage cell are concurrently read from the N−1th storage cell and the Nth storage cell to enable early restoring of bit line of the memory structure and early activating of a next word line of the memory structure;
- and
- concurrently
- receiving the bit of the Nth storage cell read by activation of the first word line and read during the N−1th consecutive read operation, and
- restoring the bit lines of the memory structure and activating the next word line.
2 more elements
Dependencies are inferred from the claim text.