# US 11,114,152 B1 · Semiconductor memory device including page buffers

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- Number: US 11,114,152 B1
- Document ID: US11114152B1
- Status: Granted
- Kind: B1
- Application number: 17/010,126
- Filed: 2020-09-02
- Granted: 2021-09-07
- Earliest claimed: 2020-04-22
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dong Hyuk Kim; Sung Lae Oh; Yeong Taek Lee; Tae Sung Park; Soo Nam Jung
- Web page: https://patentgrep.com/patent/US11114152B1

## CPC

- G11C 7/106: {Data output latches}
- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/1087: {Data input latches}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 43/40: characterised by the peripheral circuit region
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A semiconductor memory device includes a memory cell; and a page buffer including a sensing circuit that is coupled to the memory cell through a bit line. The page buffer includes a first transistor included in the sensing circuit; and a second transistor not included in the sensing circuit. A cross-sectional dimension of a first contact which is coupled to the first transistor and a cross-sectional dimension of a second contact which is coupled to the second transistor are different from each other. The cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

## Claims

### Claim 1

A semiconductor memory device comprising:
a memory cell; and
a page buffer including a sensing circuit that is coupled to the memory cell through a bit line,
the page buffer comprising:
a first transistor included in the sensing circuit; and
a second transistor not included in the sensing circuit,
wherein a cross-sectional dimension of a first contact coupled to the first transistor and a cross-sectional dimension of a second contact coupled to the second transistor are different from each other.

### Claim 2 (depends on 1)

The semiconductor memory device according to claim 1, wherein the cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

### Claim 3 (depends on 1)

The semiconductor memory device according to claim 1, wherein the first contact is coupled to a junction region of the first transistor, and the second contact is coupled to a junction region of the second transistor.

### Claim 4 (depends on 1)

The semiconductor memory device according to claim 1,
wherein the first and second transistors are disposed on a single substrate, and
wherein the first and second contacts pass through a dielectric layer that isolates the substrate and a wiring layer over the substrate and that covers the first and second transistors.

### Claim 5 (depends on 1)

The semiconductor memory device according to claim 1, wherein a channel length direction of the first transistor and a channel length direction of the second transistor is the same, and a length of the second contact is smaller than a length of the first contact in the channel length direction.

### Claim 6 (depends on 1)

The semiconductor memory device according to claim 1, wherein a distance between the second contact and a gate electrode of the second transistor is the same as a distance between the first contact and a gate electrode of the first transistor.

### Claim 7 (depends on 1)

The semiconductor memory device according to claim 1, wherein a channel length direction of the first transistor and a channel length direction of the second transistor is the same, and a length of the second transistor is smaller than a length of the first transistor in the channel length direction.

### Claim 8

A semiconductor memory device comprising:
a memory cell array defined in a memory structure stacked on a logic structure; and
a page buffer, defined in the logic structure, that includes a sensing circuit that reads data stored in the memory cell array,
the page buffer comprising:
a first transistor included in the sensing circuit; and
a second transistor not included in the sensing circuit,
wherein a cross-sectional dimension of a first contact coupled to the first transistor and a cross-sectional dimension of a second contact coupled to the second transistor are different from each other.

### Claim 9 (depends on 8)

The semiconductor memory device according to claim 8, wherein the cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

### Claim 10 (depends on 8)

The semiconductor memory device according to claim 8, wherein the first contact is coupled to a junction region of the first transistor, and the second contact is coupled to a junction region of the second transistor.

### Claim 11 (depends on 8)

The semiconductor memory device according to claim 8, wherein the first and second transistors are disposed on a single substrate, and the first and second contacts pass through a dielectric layer that isolates the substrate and a wiring layer over the substrate and that covers the first and second transistors.

### Claim 12 (depends on 8)

The semiconductor memory device according to claim 8, wherein a channel length direction of the first transistor and a channel length direction of the second transistor is the same, and a length of the second contact is smaller than a length of the first contact in the channel length direction.

### Claim 13 (depends on 8)

The semiconductor memory device according to claim 8, wherein a distance between the second contact and a gate electrode of the second transistor is the same as a distance between the first contact and a gate electrode of the first transistor.

### Claim 14 (depends on 8)

The semiconductor memory device according to claim 8, wherein a channel length direction of the first transistor and a channel length direction of the second transistor is the same, and a length of the second transistor is smaller than a length of the first transistor in the channel length direction.

### Claim 15

A semiconductor memory device comprising:
a memory cell array defined in a cell wafer; and
a page buffer, defined in a peripheral wafer bonded onto the cell wafer, that includes a sensing circuit that reads data stored in the memory cell array,
the page buffer comprising:
a first transistor included in the sensing circuit; and
a second transistor not included in the sensing circuit,
wherein a cross-sectional dimension of a first contact coupled to a junction region of the first transistor and a cross-sectional dimension of a second contact coupled to a junction region of the second transistor are different from each other.

### Claim 16 (depends on 15)

The semiconductor memory device according to claim 15, wherein the cross-sectional dimension of the second contact is smaller than the cross-sectional dimension of the first contact.

### Claim 17 (depends on 15)

The semiconductor memory device according to claim 15, wherein the first contact is coupled to a junction region of the first transistor, and the second contact is coupled to a junction region of the second transistor.

### Claim 18 (depends on 15)

The semiconductor memory device according to claim 15, wherein the first and second transistors are disposed on a single substrate, and the first and second contacts pass through a dielectric layer that isolates the substrate and a wiring layer over the substrate and that covers the first and second transistors.

### Claim 19 (depends on 15)

The semiconductor memory device according to claim 15, wherein a channel length direction of the first transistor and a channel length direction of the second transistor is the same, and a length of the second contact is smaller than a length of the first contact in the channel length direction.

### Claim 20 (depends on 15)

The semiconductor memory device according to claim 15, wherein a distance between the second contact and a gate electrode of the second transistor is the same as a distance between the first contact and a gate electrode of the first transistor.