# US 11,114,150 B2 · Memory system with multiple open rows per bank

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- Number: US 11,114,150 B2
- Document ID: US11114150B2
- Status: Granted
- Kind: B2
- Application number: 16/838,646
- Filed: 2020-04-02
- Published: 2020-10-22
- Granted: 2021-09-07
- Earliest claimed: 2019-04-18
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Thomas Vogelsang; John Eric Linstadt; Liji Gopalakrishnan
- Web page: https://patentgrep.com/patent/US11114150B2

## CPC

- G11C 11/4085: {Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C 11/4094: Bit-line management or control circuits
- G11C 14/0009: {in which the volatile element is a DRAM cell}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

## Claims

### Claim 1

A memory controller, comprising:
circuitry to associate respective indicators with a respective plurality of row address segments, the row address segments corresponding to respective row address ranges;
circuitry to set the respective indicators to a first value that is associated with the respective row address segment being unavailable for opening a row in the associated respective row address range, where a plurality of the respective indicators are set to the first value in response to at least the memory controller processing a command to a memory component to open a row in the respective row address range associated with at least one of the respective indicators; and,
circuitry to receive information, from the memory component, associating row addresses to which of the respective indicators are to be set to the first value in response to the command to the memory component to open a row.

### Claim 2 (depends on 1)

The memory controller of claim 1, wherein the memory component is a memory module comprising a plurality of memory devices and the information is communicated via a serial presence detect (SPD) communication channel.

### Claim 3 (depends on 1)

The memory controller of claim 1, wherein the controller reads the information from a DRAM integrated circuit memory device.

### Claim 4 (depends on 1)

The memory controller of claim 1, wherein the plurality of the respective indicators correspond to memory subarrays that share at least one row of sense amplifiers.

### Claim 5 (depends on 1)

The memory controller of claim 1, further comprising:
circuitry to send, to the memory component, a column access command that communicates information used to select a one of a plurality of concurrently open rows in the memory component.

### Claim 6 (depends on 5)

The memory controller of claim 5, wherein the information used to select a one of a plurality of open rows in the memory component comprises an index to a row address table on the memory component.

### Claim 7 (depends on 5)

The memory controller of claim 5, wherein a function applied to the row address is used to generate the index.

### Claim 8 (depends on 5)

The memory controller of claim 5, wherein a counter generates the index based on a number of activate row commands sent to the memory component since the last precharge command.

### Claim 9 (depends on 5)

The memory controller of claim 5, further comprising:
a table associating row addresses to index values.

### Claim 10

A method of controlling a memory component, comprising:
receiving information, from a memory component, associating row addresses of a DRAM device to respective indicators that are to be set to a first value in response to commands to the memory component to open rows, the respective indicators associated with a respective plurality of row address segments, the row address segments corresponding to respective row address ranges; and,
setting a plurality of the respective indicators to the first value, the plurality of the respective indicators are set to the first value in response to at least the memory controller processing a command to the memory component to open a first row in the respective row address range associated with at least one of the respective indicators, the first value being associated with the respective associated row address segments being unavailable for opening a second row in the associated respective row address range.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
transmitting, to the memory component, at least one command that opens a plurality of rows in the same bank.

### Claim 12 (depends on 11)

The method of claim 11, further comprising:
transmitting, to the memory component, a column access command that communicates information used to select a one of a plurality of concurrently open rows in the memory component.

### Claim 13 (depends on 12)

The method of claim 12, wherein the information used to select the one of the plurality of concurrently open rows includes an index value.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
maintaining a table of associations between row addresses and index values.

### Claim 15

A memory controller, comprising:
control circuitry to set to a first value, respective indicators in an address table that associates respective indicators with a respective plurality of row address segments, the row address segments corresponding to respective row address ranges, the first value to be associated with the respective row address segment being unavailable for opening a row in the associated respective row address range, where a plurality of the respective indicators are set to the first value in response to at least the memory controller processing a command to a memory component to open a row in the respective row address range associated with at least one of the respective indicators; and,
configuration reading circuitry to receive configuration information, from the memory component, that associates row addresses to respective indicators that are to be set to the first value in response to the command to the memory component to open a row.

### Claim 16 (depends on 15)

The memory controller of claim 15, wherein the memory component is a memory module comprising a plurality of memory devices and the configuration information is communicated via a serial presence detect (SPD) communication channel.

### Claim 17 (depends on 15)

The memory controller of claim 15, wherein the memory controller reads the configuration information from a DRAM integrated circuit memory device.

### Claim 18 (depends on 15)

The memory controller of claim 15, wherein the plurality of the respective indicators correspond to memory subarrays that share at least one row of sense amplifiers.

### Claim 19 (depends on 15)

The memory controller of claim 15, further comprising:
access circuitry to send, to the memory component, a column access command that communicates information used to select a one of a plurality of concurrently open rows in the memory component.

### Claim 20 (depends on 19)

The memory controller of claim 19, wherein the information used to select a one of a plurality of open rows in the memory component comprises an index to a row address table on the memory component.