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US 11,114,141 B2Granted
Clock generating circuit and memory device including the same
AssigneeSK hynix Inc.
InventorKwang-Soon Kim
Life of this patent
Estimating the term…
Abstract
A memory device includes a clock generating circuit suitable for generating a plurality of internal clock signals based on an external clock signal during an output period of read data, in response to a read command, and a data strobe output circuit suitable for outputting a first data strobe signal to a data strobe pad in response to the internal clock signals, wherein the internal clock signals toggle regardless of the output period of the read data, in response to a test mode signal.
Claims17
A memory device comprising:
- a clock generating circuit suitable for generating a plurality of internal clock signals based on an external clock signal during an output period of a read data, in response to a read command;
- a data strobe output circuit suitable for outputting a first data strobe signal to a data strobe pad in response to the internal clock signals;
- a data generating circuit suitable for generating a plurality of test data and outputting the generated test data as the read data, in response to a test mode signal;
- and
- a data serializing circuit suitable for serializing the read data in response to the internal clock signals,
- wherein the internal clock signals toggle regardless of the output period of the read data, in response to the test mode signal.
3 more elements
An operating method of a memory device comprising:
- activating an output enable signal indicating an output period of read data, in a test mode;
- toggling a plurality of internal clock signals based on an external clock signal, in response to the activated output enable signal;
- generating a data strobe signal and outputting the generated data strobe signal to a data strobe pad in response to the internal clock signals;
- generating a plurality of test data in the test mode;
- and
- serializing and outputting the plurality of test data to have different logic levels between neighboring test data in response to the internal clock signals.
3 more elements
A memory device comprising:
- a data strobe pad;
- a data pad;
- a clock generating circuit suitable for generating a plurality of clock signals in response to a read command to output the plurality of clock signals and toggling the plurality of clock signals in response to a test mode signal to output toggled clock signals;
- a data strobe output circuit suitable for receiving the plurality of internal clock signals or the toggled clock signals and outputting the received clock signals as a data strobe signal to the data strobe pad;
- and
- a data serializing circuit suitable for receiving read data from a memory cell array in response to the read command or test data in response to the test mode signal, serializing the received data to serialized output data and outputting the serialized output data to the data pad.
3 more elements
Dependencies are inferred from the claim text.