# US 11,114,069 B2 · Private virtualized displays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,069 B2 - Document ID: US11114069B2 - Status: Granted - Kind: B2 - Application number: 16/481,305 - Filed: 2017-12-08 - Published: 2021-05-06 - Granted: 2021-09-07 - Earliest claimed: 2017-12-08 - Assignees: Hewlett-Packard Development Company, L.P. - Applicants: Hewlett-Packard Development Company, L.P. - Inventors: Mario E Campos; Monji G Jabori; Scott Rawlings; Thong Thai - Web page: https://patentgrep.com/patent/US11114069B2 ## CPC - G06F 3/1446: {display composed of modules, e.g. video walls} - G09G 5/42: characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen - G06F 3/14: Digital output to display device {; Cooperation and interconnection of the display device with other functional units} - G06F 3/1431: {using a single graphics controller} - G06F 21/10: Protecting distributed programs or content, e.g. vending or licensing of copyrighted material (protection in video systems or pay television H04N7/16) {; Digital rights management [DRM]} - G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 5/14: Display of multiple viewports - G09G 5/391: Resolution modifying circuits, e.g. variable screen formats - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2340/14: Solving problems related to the presentation of information to be displayed - G09G 2340/145: related to small screens - G09G 2360/125: using unified memory architecture [UMA] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ## Abstract In some examples, a non-transitory machine readable medium storing instructions executable by a processor to store display information in a private memory hidden from an operating system (OS), and divisibly virtualize a contiguous planar display into a first area as a main display and a second area as a second display separate from the main display, where the continuous planar display is divisibly virtualized responsive to exposure of the display information to the OS or the display information being directly provided to a graphics processing unit (GPU). ## Claims ### Claim 1 A non-transitory machine readable medium storing instructions executable by a processor to: store display information in a private physical memory hidden from an operating system (OS); and divisibly virtualize a contiguous planar display into a first area as a main display and a second area as a second display separate from the main display, wherein the continuous planar display is divisibly virtualized responsive to: exposure of the display information in the private physical memory to the OS; or the display information being directly provided from the private physical memory to a graphics processing unit (GPU). ### Claim 2 (depends on 1) The medium of claim 1, wherein the display information includes a resolution or a display size of the second display. ### Claim 3 (depends on 1) The medium of claim 1, including instructions to expose display content to the OS when selectively exposing the display information to the OS or provide the display content directly to the GPU when directly providing the display information to the GPU. ### Claim 4 (depends on 3) The medium of claim 3, wherein the display content includes frames of variable data rate video. ### Claim 5 (depends on 3) The medium of claim 3, wherein the display content is displayed in the second area but is not displayed in the first area. ### Claim 6 (depends on 1) The medium of claim 1, further comprising instructions to expose the display information to the OS when a hidden mode is inactive. ### Claim 7 (depends on 1) The medium of claim 1, further comprising instructions to directly provide the display information from the private physical memory to the GPU when a hidden mode is active. ### Claim 8 A system, comprising: a display device having a contiguous planar display and a first interface; a computing device having a second interface to couple with the first interface of the display device, the computing device including an operating system (OS), a private random-access memory (RAM) hidden from the OS, and a processor, the processor to: store display information in the private RAM; and divisibly virtualize the contiguous planar display into a first area of the planar display as a main area and a second area isolated from the main area, wherein the continuous planar display is divisibly virtualized responsive to both an input to activate dual display mode and: exposure of the display information in the private RAM to the OS; or the display information being directly provided to a graphics processing unit (GPU). ### Claim 9 (depends on 8) The system of claim 8, further comprising an individual physical display implementing the contiguous planar display. ### Claim 10 (depends on 8) The system of claim 8, including a scaler or timing controller hardware in the display device to expose the contiguous planar display to the OS as a main GUI and a second GUI when the display information is exposed to the OS. ### Claim 11 (depends on 8) The system of claim 8, further comprising instructions to receive the input via a user interface of the contiguous planar display, activation of a physical switch, or launch of an application executing on the system. ### Claim 12 (depends on 8) The system of claim 8, wherein in the dual display mode, the system is to display in the second GUI a plurality of operable GUI controls particular to an application that currently has focus in the main GUI and that running on the computing device. ### Claim 13 (depends on 8) The system of claim 8, further comprising instructions to use the entire area of the planar display as the main area when dual display mode is inactive. ### Claim 14 A computing device comprising: a graphics processing unit (GPU); an interface to couple to a display device having a contiguous planar display a physical memory including a private frame buffer and a public frame buffer; and processor to: store display information in the private frame buffer; and responsive to an input to activate dual display mode: divisibly virtualize the contiguous planar display into a first area of the planar display as a main area and a second area isolated from the main area, wherein the continuous planar display is divisibly virtualized responsive to: selective exposure of the display information in the private frame buffer to the OS when hidden mode is inactive; or the display information being directly provided from the private frame buffer to the GPU when hidden mode is active. ### Claim 15 (depends on 14) The computing device of claim 14, wherein the computing device further comprises a dedicated switch selectable to activate or inactivate the hidden mode. ### Claim 16 (depends on 15) The computing device of claim 15, wherein the physical memory is a random-access memory (RAM).