# US 11,114,036 B2 · Scan driver and display device for driving a plurality of scan lines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,036 B2 - Document ID: US11114036B2 - Status: Granted - Kind: B2 - Application number: 16/434,432 - Filed: 2019-06-07 - Published: 2019-12-12 - Granted: 2021-09-07 - Earliest claimed: 2018-06-08 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Boyoung Chung; Youngwan Seo; Dongwoo Kim; Yeonkyung Kim; Chong Chul Chai - Web page: https://patentgrep.com/patent/US11114036B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3225: using an active matrix - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0205: Simultaneous scanning of several lines in flat panels - G09G 2310/0283: Arrangement of drivers for different directions of scanning - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A scan driver includes a plurality of circuit stages, each circuit stage including a first input part configured to transfer a carry signal to a first node in response to a first clock signal, a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node, a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node, a holding part configured to maintain a signal of a third node response to a second clock signal, and a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal. ## Claims ### Claim 1 A scan driver comprising a plurality of circuit stages cascade-connected with each other and outputting a plurality of gate signals, each of the plurality of circuit stages comprising: a first input part configured to transfer a carry signal to a first node in response to a first clock signal; a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node; a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node; a holding part configured to maintain a signal of a third node in response to a second clock signal; a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal: a first output control part configured to transfer the first clock signal to the second node in response to the first clock signal; and a second output control part configured to transfer a signal of the first node to the third node in response to a first driving voltage, wherein the second output control part comprises: an eighth transistor including a control electrode connected to a first driving voltage terminal and receiving always constant voltage that is the first driving voltage, a first electrode connected to the first node, and a second electrode connected to the third node. ### Claim 2 (depends on 1) The scan driver of claim 1, wherein the holding part comprises a sixth transistor and a seventh transistor, the sixth transistor comprises a control electrode connected to the second node, a first electrode connected to the seventh transistor and a second electrode connected to the output terminal, and the seventh transistor comprises a control electrode receiving the second clock signal, a first electrode connected to the third node and a second electrode connected to the sixth transistor. ### Claim 3 (depends on 1) The scan driver of claim 1, further comprising a simultaneous driving part configured to control the second output part in response to the third clock signal, wherein the third clock signal has a first level for a simultaneous driving period and a second level for a sequential driving period, and the simultaneous driving part is configured to apply a second level of a second driving voltage to the third node in response to the first level of the third clock signal in the simultaneous driving period. ### Claim 4 (depends on 3) The scan driver of claim 3, wherein the simultaneous driving part comprises a ninth transistor, the ninth transistor comprises a control electrode connected to a third clock terminal, a first electrode connected to a second driving voltage terminal and a second electrode connected to the first node. ### Claim 5 (depends on 3) The scan driver of claim 3, wherein the simultaneous driving part comprises a ninth transistor, the ninth transistor comprises a control electrode connected to a third clock terminal, a first electrode connected to a second driving voltage terminal and a second electrode connected to the third node. ### Claim 6 (depends on 1) The scan driver of claim 1, wherein the first output part comprises a first transistor and a first capacitor, the first transistor comprises a control electrode connected to the second node, a first electrode connected to a third clock terminal and a second electrode connected to the output terminal, and the first capacitor comprises a first electrode connected to the third clock terminal and a second electrode connected to the second node. ### Claim 7 (depends on 1) The scan driver of claim 1, wherein the second output part comprises a second transistor and a second capacitor, the second transistor comprises a control electrode connected to the third node, a first electrode connected to a second clock terminal and a second electrode connected to the output terminal, and the second capacitor comprises a first electrode connected to the output terminal and a second electrode connected to the third node. ### Claim 8 (depends on 1) The scan driver of claim 1, further comprising: a selecting part configured to output a previous scan signal outputted from a previous circuit stage of the plurality of circuit stages or a next scan signal outputted from a next circuit stage of the plurality of circuit stages to the first input part in response to a first direction signal and a second direction signal. ### Claim 9 A display device comprising: a display panel comprising a switching transistor connected to a scan line and a data line, an emission control transistor connected to the switching transistor and an organic light emitting diode; a timing controller configured to generate a first clock signal, a second clock signal different from the first clock signal and a third clock signal different from the first clock signal and the second clock signal; a scan driver configured to generate a plurality of scan signals based on the first clock signal, the second clock signal, and the third clock signal, to simultaneously output the plurality of scan signals during a simultaneous driving period and to sequentially output the plurality of scan signals during a sequential driving period, the scan driver comprises a plurality of circuit stages cascade-connected with each other, each circuit stage of the plurality of circuit stages comprising: a first input part configured to transfer a carry signal to a first node in response to a first clock signal; a second input part configured to transfer the first clock signal to a second node in response to a signal of the first node; a first output part configured to transfer a third clock signal to an output terminal in response to a signal of the second node; a holding part configured to maintain a signal of a third node in response to a second clock signal; a second output part configured to transfer a signal of the third node to the output terminal in response to the second clock signal: a first output control part configured to transfer the first clock signal to the second node in response to the first clock signal; and a second output control part configured to transfer a signal of the first node to the third node in response to a first driving voltage, wherein the second output control part comprises: an eighth transistor including a control electrode connected to a first driving voltage terminal and receiving always constant voltage that is the first driving voltage, a first electrode connected to the first node, and a second electrode connected to the third node. ### Claim 10 (depends on 9) The display device of claim 9, wherein the holding part comprises a sixth transistor and a seventh transistor, the sixth transistor comprises a control electrode connected to the second node, a first electrode connected to the seventh transistor and a second electrode connected to the output terminal, and the seventh transistor comprises a control electrode receiving the second clock signal, a first electrode connected to the third node and a second electrode connected to the sixth transistor. ### Claim 11 (depends on 9) The display device of claim 9, wherein each circuit stage of the plurality of circuit stages further comprises a simultaneous driving part configured to turn off the second output part in response to the third clock signal, wherein the third clock signal has a first level for a simultaneous driving period and a second level for a sequential driving period, and the simultaneous driving part configured to apply a second level of a second driving voltage to the third node in response to the first level of the third clock signal in the simultaneous driving period. ### Claim 12 (depends on 11) The display device of claim 11, wherein the simultaneous driving part comprises a ninth transistor, the ninth transistor comprises a control electrode connected to a third clock terminal, a first electrode connected to a second driving voltage terminal, and a second electrode connected to the first node. ### Claim 13 (depends on 11) The display device of claim 11, wherein the simultaneous driving part comprises a ninth transistor, the ninth transistor comprises a control electrode connected to the third clock terminal, a first electrode connected to a second driving voltage terminal and a second electrode connected to the third node. ### Claim 14 (depends on 9) The display device of claim 9, wherein the first output part comprises a first transistor and a first capacitor, the first transistor comprises a control electrode connected to the second node, a first electrode connected to a third clock terminal and a second electrode connected to the output terminal, and the first capacitor comprises a first electrode connected to the third clock terminal and a second electrode connected to the second node. ### Claim 15 (depends on 9) The display device of claim 9, wherein the second output part comprises a second transistor and a second capacitor, the second transistor comprises a control electrode connected to the third node, a first electrode connected to a second clock terminal and a second electrode connected to the output terminal, and the second capacitor comprises a first electrode connected to the output terminal and a second electrode connected to the third node. ### Claim 16 (depends on 9) The display device of claim 9, wherein the timing controller is configured to output a first direction signal corresponding to a forward direction scan direction and a second direction signal corresponding to a reverse direction scan direction to the scan driver, and each circuit stage of the plurality of circuit stages further comprises a selecting part configured to output a previous scan signal outputted from a previous circuit stage of the plurality of circuit stages or a next scan signal outputted from a next circuit stage of the plurality of circuit stages to the first input part in response to a first direction signal and a second direction signal.