# US 11,114,033 B2 · Pixel and display device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,033 B2 - Document ID: US11114033B2 - Status: Granted - Kind: B2 - Application number: 16/855,038 - Filed: 2020-04-22 - Published: 2021-01-28 - Granted: 2021-09-07 - Earliest claimed: 2019-07-22 - Assignees: Samsung Display Co., Ltd. - Applicants: Samsung Display Co., Ltd. - Inventors: Jun Hyun Park; Bon Yong Koo; Yu Jin Lee; Kyung Hoon Chung; Chong Chul Chai - Web page: https://patentgrep.com/patent/US11114033B2 ## CPC - G09G 3/325: the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/3241: the current through the light-emitting element being set using a data current provided by the data driver, e.g. by using a two-transistor current mirror - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3291: in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G09G 2300/0814: used for selection purposes, e.g. logical AND for partial update - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2300/0852: being a dynamic memory with more than one capacitor - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/045: Compensation of drifts in the characteristics of light emitting or modulating elements - G09G 2330/021: Power management, e.g. power saving - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A pixel including: a light emitter; a first transistor including first and second electrodes respectively connected to power and the light emitter, the first transistor controlling driving current; a first capacitor between a second and third node; a second transistor between the third node and data line and turned on by a scan signal; a third transistor between a first and second node, and turned on by a control signal; a fourth transistor between power and the third node, and turned on by a emission control signal; a fifth transistor between power and the first electrode, and turned on by the emission control signal; a sixth transistor between the second node and the light emitter, and turned on by another emission control signal; and a second capacitor between power and the first node, wherein the fourth, fifth and sixth transistors turn-on/off at least four times in a non-emission period. ## Claims ### Claim 1 A pixel, comprising: a light emitting element; a first transistor including a first electrode electrically coupled to a first power supply, and a second electrode electrically coupled to the light emitting element, the first transistor configured to control a driving current; a first capacitor coupled between a second node and a third node, wherein the second node is connected to the second electrode of the first transistor; a second transistor coupled between the third node and a data line and configured to be turned on by a scan signal; a third transistor coupled between a first node and the second node, and configured to be turned on by a control signal, wherein the first node is connected to a gate electrode of the first transistor; a fourth transistor coupled between the first power supply and the third node, and configured to be turned on by a first emission control signal; a fifth transistor coupled between the first power supply and the first electrode of the first transistor, and configured to be turned on by the first emission control signal; a sixth transistor coupled between the second node and the light emitting element, and configured to be turned on by a second emission control signal; and a second capacitor coupled between the first power supply and the first node, wherein, during a non-emission period in a frame, each of the fourth, fifth and sixth transistors repeatedly performs a turn-on operation and a turn-off operation at least four times in response to the first emission control signal or the second emission control signal. ### Claim 2 (depends on 1) The pixel according to claim 1, wherein, during the non-emission period, each of the first emission control signal and the second emission control signal includes a plurality of gate-on periods and a plurality of gate-off periods. ### Claim 3 (depends on 1) The pixel according to claim 1, wherein the non-emission period includes an on-bias period in which each of the second emission control signal and the control signal has a gate-off level and the first emission control signal has a gate-on level. ### Claim 4 (depends on 3) The pixel according to claim 3, wherein, during the on-bias period, the third and sixth transistors are turned off, and the fourth and fifth transistors are turned on. ### Claim 5 (depends on 1) The pixel according to claim 1, wherein, when the third, fourth and fifth transistors are turned on, the second and sixth transistors are turned off. ### Claim 6 (depends on 1) The pixel according to claim 1, further comprising: a seventh transistor coupled between the light emitting element and a initialization power supply and configured to be turned on by the control signal. ### Claim 7 (depends on 6) The pixel according to claim 6, wherein the non-emission period includes a first initialization period in which the initialization power supply is supplied to a fourth node between the light emitting element and the seventh transistor, a second initialization period in which the initialization power supply is supplied to the fourth node and the first node, an on-bias period in which the first transistor has an on-bias state, a compensation period in which the first transistor is diode-connected based on a voltage of the first power supply, and a write period in which the second transistor is turned on so that a data signal is supplied through the data line. ### Claim 8 (depends on 7) The pixel according to claim 7, wherein, in response to the control signal, the third transistor is turned on during the second initialization period, the compensation period, and the write period, and is turned off during the on-bias period. ### Claim 9 (depends on 7) The pixel according to claim 7 wherein, during the non-emission period, at least one of the second initialization-period the on-bias period, and the compensation period is repeated at least two times. ### Claim 10 (depends on 9) The pixel according to claim 9, wherein, during each of the first initialization period, the second initialization period, the on-bias period, and the compensation period, a switching operation of each of the fourth and fifth transistors is performed in reverse to a switching operation of the sixth transistor. ### Claim 11 (depends on 9) The pixel according to claim 9, wherein, during the second initialization period, the third, sixth, and seventh transistors are turned on and the fourth and fifth transistors are turned off, so that the first transistor has an off-bias state. ### Claim 12 (depends on 9) The pixel according to claim 9, wherein, during the compensation period, the third, fourth and fifth transistors are tuned on and the second and sixth transistors are turned off, and wherein, during the write period, the second and third transistors are turned on, and the fourth, fifth and sixth transistors are turned off. ### Claim 13 (depends on 7) The pixel according to claim 7, wherein a length of the compensation period is greater that a length of the write period. ### Claim 14 (depends on 7) The pixel according to claim 7, wherein, during the write period, a gate-off period of the control signal overlaps with a portion of a gate-on period of the scan signal, and wherein, while the second transistor remains turned on during the write period, the third transistor is turned off. ### Claim 15 (depends on 7) The pixel according to claim 7, wherein the first emission control signal is obtained by shifting the second emission control signal by k horizontal cycles, wherein k is an integral number greater than or equal to 3. ### Claim 16 A display device, comprising: a display panel including a plurality of pixels; a first scan driver configured to supply a scan signal to the pixels through a plurality of scan lines; a second scan driver configured to supply a control signal to the pixels through a plurality of control lines; an emission driver configured to supply an emission control signal to the pixels through a plurality of emission control lines; and a data driver configured to supply a data voltage to the display panel through a plurality of data lines, wherein each of the pixels comprises: a light emitting element; a first transistor including a first electrode electrically coupled to a first power supply, and a second electrode electrically coupled to the light emitting element, the first transistor configured to control a driving current; a first capacitor coupled between a second node and a third node, wherein the second node is connected to the second electrode of the first transistor; a second transistor coupled between the third node and a corresponding one of the data lines and configured to be turned on by the scan signal; a third transistor coupled between a first node and the second node and configured to be turned on by the control signal, wherein the first node is connected to a gate electrode of the first transistor; a fourth transistor coupled between the first power supply and the third node, and configured to be turned on by the emission control signal; a fifth transistor coupled between the first power supply and the first electrode of the first transistor, and configured to be turned on by the emission control signal; a sixth transistor coupled between the second node and the light emitting element, and configured to be turned on by a preceding emission control signal; a seventh transistor coupled between the light emitting element and an initialization power supply, and configured to be turned on by the control signal; and a second capacitor coupled between the first power supply and the first node, wherein, during a non-emission period in a frame, each of the fourth, fifth and sixth transistors repeatedly performs a turn-on operation and a turn-off operation at least four times. ### Claim 17 (depends on 16) The display device according to claim 16, wherein the non-emission period includes an on-bias period in Which each of the preceding emission control signal and the control signal has a gate-off level and the emission control signal has a gate-on level, and wherein, during the on-bias period, the third and sixth transistors are turned off, and the fourth and fifth transistors are turned on. ### Claim 18 (depends on 16) The display device according to claim 16, wherein the emission driver simultaneously supplies the emission control signal to the fourth and fifth transistors of an n-th pixel disposed on an n-th pixel row and to the fourth and fifth transistors of an n+1-th pixel disposed on an n+1-th pixel row. ### Claim 19 (depends on 18) The display device according to claim 18, wherein the second scan driver simultaneously supplies the control signal to the third and seventh transistors of the n-th pixel and to the third and seventh transistors of the n+1-th pixel. ### Claim 20 (depends on 16) The display device according to claim 16, wherein the non-emission period includes an off bias period in which each of the preceding emission control signal and the control signal has a gate-on level and the emission control signal has a gate-off level, and wherein, during the off-bias period, the third and sixth transistors are turned on, the fourth and fifth transistors are turned on, and the first transistor has an off-bias state. ### Claim 21 A pixel, comprising: a light emitting element; a first transistor including a first electrode electrically coupled to a first power supply, and a second electrode electrically coupled to the light emitting element, the first transistor configured to control a driving current; a first capacitor coupled to the second electrode of the first transistor; a second transistor coupled between a data line and the first capacitor and configured to be turned on by a scan signal; a third transistor coupled between a gate electrode of the first transistor and the second electrode of the first transistor; a fourth transistor coupled between the first power supply and the first capacitor, and configured to be turned on by a first emission control signal; a fifth transistor coupled between the first power supply and the first electrode of the first transistor, and configured to be turned on by the first emission control signal; a sixth transistor coupled between the second electrode of the first transistor and the light emitting element, and configured to be turned on by a second emission control signal; and a second capacitor coupled between the first power supply and the gate electrode of the first transistor, wherein, during a non-emission period in a frame, each of the fourth, fifth and sixth transistors repeatedly performs a tuna-on operation and a turn-off operation at least four times in response to the first emission control signal or the second emission control signal.