# US 11,114,004 B2 · Gate driving unit, driving method thereof, gate driving circuit and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,114,004 B2 - Document ID: US11114004B2 - Status: Granted - Kind: B2 - Application number: 16/094,615 - Filed: 2018-03-14 - Published: 2021-07-22 - Granted: 2021-09-07 - Earliest claimed: 2017-04-21 - Assignees: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Applicants: Beijing Boe Optoelectronics Technology Co., Ltd.; Boe Technology Group Co., Ltd. - Inventors: Yan Li; Lingyun Shi; Wei Sun; Xiaobo Xie; Meiling Jin - Web page: https://patentgrep.com/patent/US11114004B2 ## CPC - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/08: Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/06: Details of flat display driving waveforms - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2330/021: Power management, e.g. power saving - G09G 2330/023: using energy recovery or conservation - G09G 2340/0407: Resolution change, inclusive of the use of different resolutions for different screen areas - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract The present disclosure provides a gate driving unit, a driving method thereof, a gate driving circuit and a display device. The gate driving unit includes an input resetting module, a storage module, a pull-up node control module, a pull-down node control module and an output module. The gate driving unit further includes a clock signal control module, connected to a first control signal end, a second control signal end, a first reference clock signal end, a second reference clock signal end, a first clock signal end and a second clock signal end, and configured to, under the control of a first control signal from the first control signal end and a second control signal from the second control signal end, output clock signals at a same frequency and in opposite phases to the first clock signal end and the second clock signal end respectively in accordance with a first reference clock signal from the first reference clock signal end and a second reference clock signal from the second reference clock signal. ## Claims ### Claim 1 A gate driving unit, comprising an input resetting module, a storage module, a pull-up node control module, a pull-down node control module and an output module, wherein the input resetting module is connected to a pull-up node, the pull-up node control module is connected to a pull-down node and the pull-up node, and the storage module is connected to the pull-up node and a gate driving signal output end; the pull-down node control module is connected to a first clock signal end, the pull-up node and the pull-down node, and configured to control the pull-down node to be electrically connected to the first clock signal end when a potential at the pull-up node is a first level and a second level is applied to the first clock signal end; the output module is connected to the pull-up node, the pull-down node, a second clock signal end and the gate driving signal output end, and configured to control the gate driving signal output end to be electrically connected to the second clock signal end when the potential at the pull-up node is a second level; and the gate driving unit further comprises a clock signal control module connected to a first control signal end, a second control signal end, a first reference clock signal end, a second reference clock signal end, the first clock signal end and the second clock signal end, and configured to, under the control of a first control signal from the first control signal end and a second control signal from the second control signal end, output clock signals at a same frequency and in opposite phases to the first clock signal end and the second clock signal end at the same time respectively in accordance with a first reference clock signal from the first reference clock signal end and a second reference clock signal from the second reference clock signal end. ### Claim 2 (depends on 1) The gate driving unit according to claim 1, wherein the first reference clock signal and the second reference clock signal are at a same frequency and in opposite phases. ### Claim 3 (depends on 1) The gate driving unit according to claim 1, wherein the clock signal control module comprises: a first switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the first reference clock signal end, and a second electrode of which is connected to the first clock signal end; a second switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the first clock signal end, and a second electrode of which is connected to the second reference clock signal end; a third switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the second reference clock signal end, and a second electrode of which is connected to the second clock signal end; and a fourth switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the second clock signal end, and a second electrode of which is connected to the first reference clock signal end. ### Claim 4 (depends on 1) The gate driving unit according to claim 1, wherein the clock signal control module comprises: a first switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the first reference clock signal end, and a second electrode of which is connected to the first clock signal end; a second switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the first clock signal end, and a second electrode of which is connected to the second reference clock signal end; and an inverter, an input end of which is connected to the first clock signal end, and an output end of which is connected to the second clock signal end. ### Claim 5 (depends on 1) The gate driving unit according to claim 1, wherein the pull-down node control module is further connected to the gate driving signal output end and a first level input end, and further configured to control the pull-down node to be electrically connected to the first level input end when the potential at the pull-up node is the second level, and control the pull-down node to be electrically connected to the first level input end when the a gate driving signal from the gate driving signal output end is at the second level; and the output module is further connected to the first level input end, and further configured to control the gate driving signal output end to be electrically connected to the first level input end when a potential at the pull-down node is the second level. ### Claim 6 (depends on 5) The gate driving unit according to claim 5, wherein the pull-down node control module comprises: a first pull-down node control transistor, a gate electrode of which is connected to the pull-up node, a first electrode of which is connected to the first level input end, and a second electrode of which is connected to the pull-down node; a second pull-down node control transistor, a gate electrode of which is connected to the gate driving signal output end, a first electrode of which is connected to the pull-down node, and a second electrode of which is connected to the first level input end; a third pull-down node control transistor, a gate electrode and a first electrode of which are connected to the first clock signal end, and a second electrode of which is connected to the pull-down node; and a pull-down node potential maintenance capacitor, a first end of which is connected to the pull-down node, and a second end of which is connected to the first level input end. ### Claim 7 (depends on 5) The gate driving unit according to claim 5, wherein the output module comprises: a pull-up transistor, a gate electrode of which is connected to the pull-up node, a first electrode of which is connected to the second clock signal end, and a second electrode of which is connected to the gate driving signal output end; and a pull-down transistor, a gate electrode of which is connected to the pull-down node, a first electrode of which is connected to the gate driving signal output end, and a second electrode of which is connected to the first level input end. ### Claim 8 (depends on 1) The gate driving unit according to claim 1, wherein the input resetting module comprises: an inputting transistor, a gate electrode of which is connected to an input end, a first electrode of which is connected to a first scanning level input end, and a second electrode of which is connected to the pull-up node; and a resetting transistor, a gate electrode of which is connected to a resetting end, a first electrode of which is connected to the pull-up node, and a second electrode of which is connected to a second scanning level input end. ### Claim 9 (depends on 1) The gate driving unit according to claim 1, wherein the storage module comprises a storage capacitor, a first end of which is connected to the pull-up node, and a second end of which is connected to the gate driving signal output end. ### Claim 10 (depends on 1) The gate driving unit according to claim 1, wherein the pull-up node control module comprises a pull-up node control transistor, a gate electrode of which is connected to the pull-down node, a first electrode of which is connected to the pull-up node, and a second electrode of which is connected to the first level input end. ### Claim 11 (depends on 1) A method for driving the gate driving unit according to claim 1, comprising: at a low power consumption display stage, under the control of the first control signal and the second control signal, applying, by the clock signal control module, the first clock signal to the first clock signal input end and applying the second clock signal to the second clock signal input end in accordance with the first reference clock signal and the second reference clock signal, the first clock signal and the second clock signal being at a same frequency and in opposite phases, the first control signal and the second control signal being each a signal at a fixed level; and at a high definition display stage, under the control of the first control signal and the second control signal, applying, by the clock signal control module, a third clock signal to the first clock signal input end and applying a fourth clock signal to the second clock signal input end in accordance with the first reference clock signal and the second reference clock signal, the third clock signal and the fourth clock signal being at a same frequency and in opposite phases, the first control signal and the second control signal being at a same frequency, the first reference clock signal and the second reference clock signal being at a same frequency and in opposite phases, each of the first reference clock signal and the second reference clock signal having a period of T, the first control signal being delayed by T/4 relative to the first reference clock signal, and the third clock signal having a frequency greater than the first clock signal. ### Claim 12 A gate driving circuit, comprising a plurality of gate driving units, wherein the gate driving units are connected to each other in a cascaded manner, each of the gate driving units comprising an input resetting module, a storage module, a pull-up node control module, a pull-down node control module and an output module, wherein the input resetting module is connected to a pull-up node, the pull-up node control module is connected to a pull-down node and the pull-up node, and the storage module is connected to the pull-up node and a gate driving signal output end; the pull-down node control module is connected to a first clock signal end, the pull-up node and the pull-down node, and configured to control the pull-down node to be electrically connected to the first clock signal end when a potential at the pull-up node is a first level and a second level is applied to the first clock signal end; the output module is connected to the pull-up node, the pull-down node, a second clock signal end and the gate driving signal output end, and configured to control the gate driving signal output end to be electrically connected to the second clock signal end when the potential at the pull-up node is a second level; and the gate driving unit further comprises a clock signal control module connected to a first control signal end, a second control signal end, a first reference clock signal end, a second reference clock signal end, the first clock signal end and the second clock signal end, and configured to, under the control of a first control signal from the first control signal end and a second control signal from the second control signal end, output clock signals at a same frequency and in opposite phases to the first clock signal end and the second clock signal end at the same time respectively in accordance with a first reference clock signal from the first reference clock signal end and a second reference clock signal from the second reference clock signal end. ### Claim 13 (depends on 12) A display device, comprising the gate driving circuit according to claim 12. ### Claim 14 (depends on 12) The gate driving circuit according to claim 12, wherein the first reference clock signal and the second reference clock signal are at a same frequency and in opposite phases. ### Claim 15 (depends on 12) The gate driving circuit according to claim 12, wherein the clock signal control module comprises: a first switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the first reference clock signal end, and a second electrode of which is connected to the first clock signal end; a second switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the first clock signal end, and a second electrode of which is connected to the second reference clock signal end; a third switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the second reference clock signal end, and a second electrode of which is connected to the second clock signal end; and a fourth switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the second clock signal end, and a second electrode of which is connected to the first reference clock signal end. ### Claim 16 (depends on 12) The gate driving circuit according to claim 12, wherein the clock signal control module comprises: a first switching transistor, a gate electrode of which is connected to the first control signal end, a first electrode of which is connected to the first reference clock signal end, and a second electrode of which is connected to the first clock signal end; a second switching transistor, a gate electrode of which is connected to the second control signal end, a first electrode of which is connected to the first clock signal end, and a second electrode of which is connected to the second reference clock signal end; and an inverter, an input end of which is connected to the first clock signal end, and an output end of which is connected to the second clock signal end. ### Claim 17 (depends on 12) The gate driving circuit according to claim 12, wherein the pull-down node control module is further connected to the gate driving signal output end and a first level input end, and further configured to control the pull-down node to be electrically connected to the first level input end when the potential at the pull-up node is the second level, and control the pull-down node to be electrically connected to the first level input end when the a gate driving signal from the gate driving signal output end is at the second level; and the output module is further connected to the first level input end, and further configured to control the gate driving signal output end to be electrically connected to the first level input end when a potential at the pull-down node is the second level. ### Claim 18 (depends on 17) The gate driving circuit according to claim 17, wherein the pull-down node control module comprises: a first pull-down node control transistor, a gate electrode of which is connected to the pull-up node, a first electrode of which is connected to the first level input end, and a second electrode of which is connected to the pull-down node; a second pull-down node control transistor, a gate electrode of which is connected to the gate driving signal output end, a first electrode of which is connected to the pull-down node, and a second electrode of which is connected to the first level input end; a third pull-down node control transistor, a gate electrode and a first electrode of which are connected to the first clock signal end, and a second electrode of which is connected to the pull-down node; and a pull-down node potential maintenance capacitor, a first end of which is connected to the pull-down node, and a second end of which is connected to the first level input end. ### Claim 19 (depends on 17) The gate driving circuit according to claim 17, wherein the output module comprises: a pull-up transistor, a gate electrode of which is connected to the pull-up node, a first electrode of which is connected to the second clock signal end, and a second electrode of which is connected to the gate driving signal output end; and a pull-down transistor, a gate electrode of which is connected to the pull-down node, a first electrode of which is connected to the gate driving signal output end, and a second electrode of which is connected to the first level input end. ### Claim 20 (depends on 12) The gate driving circuit according to claim 12, wherein the input resetting module comprises: an inputting transistor, a gate electrode of which is connected to an input end, a first electrode of which is connected to a first scanning level input end, and a second electrode of which is connected to the pull-up node; and a resetting transistor, a gate electrode of which is connected to a resetting end, a first electrode of which is connected to the pull-up node, and a second electrode of which is connected to a second scanning level input end, wherein the storage module comprises a storage capacitor, a first end of which is connected to the pull-up node, and a second end of which is connected to the gate driving signal output end, wherein the pull-up node control module comprises a pull-up node control transistor, a gate electrode of which is connected to the pull-down node, a first electrode of which is connected to the pull-up node, and a second electrode of which is connected to the first level input end.