# US 11,113,446 B2 · Yield improving leaf cells optimization for semiconductor netlists > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,446 B2 - Document ID: US11113446B2 - Status: Granted - Kind: B2 - Application number: 16/747,009 - Filed: 2020-01-20 - Published: 2021-07-22 - Granted: 2021-09-07 - Earliest claimed: 2020-01-20 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Thomas Makowski; Matthias Ringe; Andreas H. A. Arp; Michael V. Koch; Fatih Cilek - Web page: https://patentgrep.com/patent/US11113446B2 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 2119/06: Power analysis or power optimisation - G06F 2119/12: Timing analysis or timing optimisation - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer system improves a production yield of a semiconductor chip described by design data. The computer system includes a synthesis controller in signal communication with a yield optimization controller. The synthesis controller generates design data representing a design implementation of the semiconductor chip. The yield optimization controller extracts timing information from the design data. The timing information describes a slack related to a timing path within the semiconductor chip. The yield optimization controller further identifies one or more one yield improvable cells described by the design data, and determines from the design data an adverse impact of yield improvement on the slack. Based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the yield improvable cell, and modifies the subset of the yield improvable cell so that the production yield is improved. ## Claims ### Claim 1 A computer-implemented method for improving a production yield of a semiconductor chip described by design data, the method comprising: extracting, via a yield optimization controller, timing information from the design data, the timing information describing a slack related to a timing path within the semiconductor chip; identifying, via a yield optimization controller, at least one yield improvable cell described by the design data; determining, via a yield optimization controller, from the design data an adverse impact of yield improvement on the slack; based on the timing information and the determined adverse impact, calculating, via a yield optimization controller, a subset of the at least one yield improvable cell; and modifying, via a yield optimization controller, the subset of the at least one yield improvable cell by modifying the design data such that a region within a metal layer surrounding a via described by the design data is enlarged so that the production yield is improved without reducing the slack below a targeted slack threshold value. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, wherein enlarging the region includes increasing an overlap of the region that includes the via. ### Claim 3 (depends on 1) The computer-implemented method of claim 1, wherein calculating the subset of the at least one yield improvable cell includes optimizing a target function describing an overall production yield as a function of the subset to be calculated. ### Claim 4 (depends on 3) The computer-implemented method of claim 3, wherein the subset of the at least one yield improvable cell is calculated based at least in part on constraints derived from the timing information and the adverse impact of yield improvement on the slack. ### Claim 5 (depends on 1) The computer-implemented method of claim 1, wherein modifying the subset of the at least one yield improvable cell comprises modifying the subset of yield improvable cells by switching the timing improved cells to yield improved cells with metal enlarged around the vias. ### Claim 6 A computer system configured to improve a production yield of a semiconductor chip described by design data comprises: a synthesis controller configured to generate design data representing a design implementation of the semiconductor chip; a yield optimization controller in signal communication with the synthesis controller, the yield optimization controller configured to extract timing information from the design data, the timing information describing a slack related to a timing path within the semiconductor chip, identify at least one yield improvable cell described by the design data, and determine from the design data an adverse impact of yield improvement on the slack, wherein based on the timing information and the determined adverse impact, the yield optimization controller calculates a subset of the at least one yield improvable cell; and modifies the subset of the at least one yield improvable cell so that the production yield is improved, wherein the yield optimization controller modifies the subset of the at least one yield improvable cell comprises in response to modifying the design data such that a region within a metal layer surrounding a via described by the design data is enlarged to improve the production yield without reducing the slack below a targeted slack threshold value. ### Claim 7 (depends on 6) The computer system of claim 6, wherein the yield optimization controller in response to increasing an overlap of the region that includes the via. ### Claim 8 (depends on 6) The computer system of claim 6, wherein the yield optimization controller calculates the subset of the at least one yield improvable cell in response to optimizing a target function describing an overall production yield as a function of the subset to be calculated. ### Claim 9 (depends on 8) The computer system of claim 8, wherein the subset of the at least one yield improvable cell is calculated based at least in part on constraints derived from the timing information and the adverse impact of yield improvement on the slack. ### Claim 10 (depends on 6) The computer system of claim 6, wherein modifying the subset of the at least one yield improvable cell comprises modifying the subset of yield improvable cells by switching the timing improved cells to yield improved cells with metal enlarged around the vias. ### Claim 11 A computer program product for improving a production yield of a semiconductor chip described by design data, the computer program product comprising: a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising: extracting, via a yield optimization controller, timing information from the design data, the timing information describing a slack related to a timing path within the semiconductor chip; identifying, via a yield optimization controller, at least one yield improvable cell described by the design data; determining, via a yield optimization controller, from the design data an adverse impact of yield improvement on the slack; based on the timing information and the determined adverse impact, calculating, via a yield optimization controller, a subset of the at least one yield improvable cell; and modifying, via a yield optimization controller, the subset of the at least one yield improvable cell by modifying the design data such that a region within a metal layer surrounding a via described by the design data is enlarged so that the production yield is improved without reducing the slack below a targeted slack threshold value. ### Claim 12 (depends on 11) The computer program product of claim 11, wherein enlarging the region includes increasing an overlap of the region that includes the via. ### Claim 13 (depends on 11) The computer program product of claim 11, wherein calculating the subset of the at least one yield improvable cell includes optimizing a target function describing an overall production yield as a function of the subset to be calculated. ### Claim 14 (depends on 13) The computer program product of claim 13, wherein the subset of the at least one yield improvable cell is calculated based at least in part on constraints derived from the timing information and the adverse impact of yield improvement on the slack. ### Claim 15 (depends on 1, 11) The computer program product of claim 11, The computer-implemented method of claim 1, wherein modifying the subset of the at least one yield improvable cell comprises modifying the subset of yield improvable cells by switching the timing improved cells to yield improved cells with metal enlarged around the vias.