# US 11,113,443 B1 · Integrated circuit with thicker metal lines on lower metallization layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,443 B1 - Document ID: US11113443B1 - Status: Granted - Kind: B1 - Application number: 16/900,684 - Filed: 2020-06-12 - Granted: 2021-09-07 - Earliest claimed: 2020-06-12 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Kuang-Hung Chang; Yuan-Te Hou; Chung-Hsing Wang; Yung-Chin Hou - Web page: https://patentgrep.com/patent/US11113443B1 ## CPC - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H10W 20/42: Vias, e.g. via plugs - G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30) - G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist - G06F 30/394: Routing (G06F30/396 takes precedence) - H10D 84/834: {comprising FinFETs} - H10W 20/43: Layouts of interconnections - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - G06F 30/337: Design optimisation - G06F 30/373: Design optimisation - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - H10D 30/62: Fin field-effect transistors [FinFET] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An IC structure includes first, second, third and fourth transistors on a substrate, and first and second metallization layers over the transistors. The first metallization layer has a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction. One or more of the first metal lines are part of a first net electrically connecting the first and second transistors. The second metallization layer has a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction and less than the first line width. One or more of the second metal lines are part of a second net electrically connecting the third and fourth transistors, and a total length of the second net is less than a total length of the first net. ## Claims ### Claim 1 An integrated circuit (IC) structure, comprising: a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate; a first metallization layer above the first, second, third and fourth transistors, the first metallization layer having a plurality of first metal lines extending laterally along a first direction and having a first line width measured in a second direction perpendicular to the first direction, each of the plurality of first metal lines having a first length measured along the first direction, wherein one or more of the plurality of first metal lines are part of a first net electrically connecting the first transistor and the second transistor; and a second metallization layer over the first metallization layer, the second metallization layer having a plurality of second metal lines extending laterally along the second direction and having a second line width measured in the first direction, each of the plurality of second metal lines having a second length measured along the second direction, wherein the second line width of the second metal lines is less than the first line width of the first metal lines, one or more of the plurality of second metal lines are part of a second net electrically connecting the third transistor and the fourth transistor, and a total length of the second lengths of the one or more of the plurality of the second metal lines in the second net is less than a total length of the first lengths of the one or more of the plurality of the first metal lines in the first net. ### Claim 2 (depends on 1) The IC structure of claim 1, further comprising: a third metallization layer below the first metallization layer, the third metallization layer having a plurality of third metal lines extending along the second direction and having a third line width measured in the first direction, wherein the third line width of the third metal lines is less than the first line width of the first metal lines. ### Claim 3 (depends on 2) The IC structure of claim 2, wherein the third line width of the third metal lines is greater than the second line width of the second metal lines. ### Claim 4 (depends on 2) The IC structure of claim 2, further comprising: a fourth metallization layer over the second metallization layer, the fourth metallization layer comprising a plurality of fourth metal lines extending along the first direction and having a fourth line width measured in the second direction, wherein the fourth line width of the fourth metal lines is less than the first line width of the first metal lines. ### Claim 5 (depends on 4) The IC structure of claim 4, wherein the fourth line width of the fourth metal lines is greater than the second line width of the second metal lines. ### Claim 6 (depends on 4) The IC structure of claim 4, wherein the fourth line width of the fourth metal lines is the same as the third line width of the third metal lines. ### Claim 7 (depends on 2) The IC structure of claim 2, further comprising: a fourth metallization layer below the third metallization layer, the fourth metallization layer comprising a plurality of fourth metal lines extending along the first direction and having a fourth line width measured in the second direction, wherein the fourth line width of the fourth metal lines is less than the third line width of the third metal lines. ### Claim 8 (depends on 7) The IC structure of claim 7, wherein the fourth line width of the fourth metal lines is the same as the second line width of the second metal lines. ### Claim 9 (depends on 1) The IC structure of claim 1, further comprising: a third metallization layer over the second metallization layer, the third metallization layer having a plurality of third metal lines extending along the second direction and having a third line width measured in the first direction, wherein the third line width of the third metal lines is greater than the second line width of the second metal lines. ### Claim 10 (depends on 9) The IC structure of claim 9, wherein the third line width of the third metal lines is the same as the first line width of the first metal lines. ### Claim 11 (depends on 1) The IC structure of claim 1, wherein the first, second, third and fourth transistors are fin field-effect transistors (FinFETs). ### Claim 12 An integrated circuit (IC) structure, comprising: a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate; a first metallization layer above the first, second, third and fourth transistors, the first metallization layer comprising a plurality of first metal lines extending laterally along a first direction and arranged at a first line-to-line spacing, wherein the plurality of first metal lines each have a first length measured along the first direction, and one or more of the plurality of first metal lines are part of a first net electrically connecting the first transistor and the second transistor; and a second metallization layer over the first metallization layer, the second metallization layer comprising a plurality of second metal lines extending laterally along a second direction perpendicular to the first direction and arranged at a second line-to-line spacing, wherein the plurality of second metal lines each have a second length measured along the second direction, the first line-to-line spacing is greater than the second line-to-line spacing, one or more of the plurality of second metal lines are part of a second net connecting the third transistor and the fourth transistor, and a total length of the second lengths of the plurality of second metal lines in the second net is less than a total length of the first lengths of the plurality of first metal lines in the first net. ### Claim 13 (depends on 12) The IC structure of claim 12, further comprising: a third metallization layer over the second metallization layer, the third metallization layer comprising a plurality of third metal lines extending along the first direction and arranged at a third line-to-line spacing, wherein the third line-to-line spacing is greater than the second line-to-line spacing. ### Claim 14 (depends on 13) The IC structure of claim 13, wherein the third line-to-line spacing is the same as the first line-to-line spacing. ### Claim 15 (depends on 12) The IC structure of claim 12, further comprising: a third metallization layer below the first metallization layer, the third metallization layer extending along the second direction and arranged at a third line-to-line spacing, wherein the third line-to-line spacing is less than the first line-to-line spacing. ### Claim 16 (depends on 15) The IC structure of claim 15, wherein the third line-to-line spacing is the same as the second line-to-line spacing. ### Claim 17 An integrated circuit (IC) structure, comprising: a first transistor, a second transistor, a third transistor and a fourth transistor formed on a substrate; a first metallization layer above the first, second, third and fourth transistors, the first metallization layer having a plurality of first metal lines extending laterally along a first direction and having a first line height measured vertically in a second direction perpendicular to the first direction, wherein the plurality of first metal lines each have a first length measured along the first direction, and one or more of the plurality of first metal lines are part of a first net electrically connecting the first transistor and the second transistor; and a second metallization layer over and next to the first metallization layer, the second metallization layer having a plurality of second metal lines extending laterally along a third direction perpendicular to the first and second directions, the plurality of second metal lines having a second line height measured vertically in the second direction, wherein the plurality of second metal lines each have a second length measured along the third direction, the second line height of the plurality of second metal lines is less than the first line height of the plurality of first metal lines, one or more of the plurality of second metal lines are part of a second net electrically connecting the third transistor and the fourth transistor, and a total length of the second length of the plurality of second metal lines in the second net is less than a total length of the first length of the plurality of first metal lines in the first net. ### Claim 18 (depends on 17) The IC structure of claim 17, further comprising: a third metallization layer over and next to the second metallization layer, the third metallization layer having a plurality of third metal lines extending laterally along the first direction, the plurality of third metal lines having a third line height measured vertically in the second direction, wherein the third line height of the plurality of third metal lines is greater than the second line height of the plurality of second metal lines. ### Claim 19 (depends on 18) The IC structure of claim 18, wherein the third line height of the plurality of third metal lines is less than the first line height of the plurality of first metal lines. ### Claim 20 (depends on 17) The IC structure of claim 17, further comprising: a third metallization layer below and next to the first metallization layer, the third metallization layer having a plurality of third metal lines extending laterally along the third direction, the plurality of third metal lines having a third line height measured vertically in the second direction, wherein the third line height of the plurality of third metal lines is greater than the second line height of the plurality of second metal lines and less than the first line height of the plurality of first metal lines.