# US 11,113,442 B2 · Methods and apparatus for reducing reliability degradation on an integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,442 B2 - Document ID: US11113442B2 - Status: Granted - Kind: B2 - Application number: 15/718,685 - Filed: 2017-09-28 - Published: 2019-03-28 - Granted: 2021-09-07 - Earliest claimed: 2017-09-28 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Ning Cheng; Xiangyong Wang; Mahesh A. Iyer - Web page: https://patentgrep.com/patent/US11113442B2 ## CPC - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 30/394: Routing (G06F30/396 takes precedence) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 2119/02: Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA] - G06F 2119/04: Ageing analysis or optimisation against ageing - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An integrated circuit with programmable logic circuitry is provided. The integrated circuit may include quiet regions, toggling regions, or unused regions. An integrated circuit may also include heavily-used metal routing paths, lightly-used metal routing paths, and unused metal routing paths. Circuit design tools may be used to generate multiple configuration images that replace the quiet regions with toggling or unused regions, that swap the heavily-used metal routing paths with lightly-used or unused metal routing paths, or that use random fitter seeds of improve the usage coverage to statistically reduce the always quiet regions on the integrated circuit. The multiple configuration images implement the same design and can be used to reconfigure the integrated circuit upon startup to reduce aging effects and improve circuit performance. ## Claims ### Claim 1 A method of using integrated circuit design tools to implement a circuit design on an integrated circuit, the method comprising: with the integrated circuit design tools, generating a first configuration image to implement the circuit design using a first random fitter seed to perform place and route; with the integrated circuit design tools, generating a second configuration image that is different than the first configuration image using a second random fitter seed that is different than the first random fitter seed to perform place and route, wherein the second configuration image implements the circuit design; configuring the integrated circuit using the first configuration image; and reconfiguring the integrated circuit using the second configuration image. ### Claim 2 (depends on 1) The method of claim 1, further comprising: generating a physical netlist for the circuit design; and running functional simulation on the physical netlist to obtain signal activity profile data. ### Claim 3 (depends on 2) The method of claim 2, further comprising analyzing the signal activity profile data to identify a quiet region and a toggling region in the circuit design. ### Claim 4 (depends on 3) The method of claim 3, further comprising analyzing the signal activity profile data to identify an unused region in the circuit design. ### Claim 5 (depends on 4) The method of claim 4, wherein generating the second configuration image comprises replacing the quiet region with a selected one of the toggling region and the unused region to reduce aging on the integrated circuit. ### Claim 6 (depends on 3) The method of claim 3, further comprising analyzing the signal activity profile data to identify a heavily-used conductive routing path and a lightly-used conductive routing path. ### Claim 7 (depends on 6) The method of claim 6, wherein generating the second configuration image comprises swapping the heavily-used conductive routing path with the lightly-used conductive routing path to reduce electromigration on the integrated circuit. ### Claim 8 (depends on 1) The method of claim 1, wherein: the first configuration image has a first set of quiet regions; and wherein the second configuration image has a second set of quiet regions that is at least partially non-overlapping with the first set of quiet regions. ### Claim 9 (depends on 1) The method of claim 1, wherein the first and second configuration images comprise partial reconfiguration images. ### Claim 10 A method of using integrated circuit design tools to implement a circuit design on an integrated circuit, the method comprising: with the integrated circuit design tools, generating a first configuration image to implement the circuit design using a first random fitter seed to perform place and route, wherein the first configuration image has a first set of unused regions; with the integrated circuit design tools, generating a second configuration image that is different than the first configuration image using a second random fitter seed that is different than the first random fitter seed to perform place and route, wherein the second configuration image implements the circuit design, and wherein the second configuration image has a second set of unused regions that is at least partially non-overlapping with the first set of unused regions; configuring the integrated circuit using the first configuration image; and reconfiguring the integrated circuit using the second configuration image. ### Claim 11 (depends on 10) The method of claim 10, further comprising: generating a physical netlist for the circuit design; and running functional simulation on the physical netlist to obtain signal activity profile data. ### Claim 12 (depends on 10) The method of claim 10, wherein the first and second configuration images comprise partial reconfiguration images. ### Claim 13 (depends on 10) The method of claim 10 further comprising: generating a third configuration image that is different than the first and second configuration images, wherein the third configuration image implements the circuit design; and reconfiguring the integrated circuit using the third configuration image. ### Claim 14 A non-transitory computer-readable storage medium comprising instructions for: generating a first configuration image to implement a circuit design using a first random fitter seed; generating a second configuration image that is different than the first configuration image using a second random fitter seed that is different than the first random fitter seed, wherein the second configuration image implements the same circuit design as the first configuration image; and configuring an integrated circuit using the first configuration image; reconfiguring the integrated circuit using the second configuration image. ### Claim 15 (depends on 14) The non-transitory computer-readable storage medium of claim 14, further comprising instructions for: generating a physical netlist; performing functional simulation on the physical netlist to obtain activity profile data; and analyzing the activity profile data to identify first and second different region types in the circuit design, wherein generating the second configuration image comprises replacing the first region type with the second region type. ### Claim 16 (depends on 14) The non-transitory computer-readable storage medium of claim 14, further comprising instructions for: identifying first and second different metal types in the circuit design, wherein generating the second configuration image comprises swapping the first and second different metal types. ### Claim 17 (depends on 14) The non-transitory computer-readable storage medium of claim 14, further comprising instructions for: generating a third configuration image that is different than the first and second configuration images, wherein the third configuration image also implements the same circuit design as the first and second configuration images; and taking turns reconfiguring the integrated circuit using at least the first, second, and third configuration images in response to restarting the integrated circuit. ### Claim 18 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the first configuration image has a first set of quiet regions, and the second configuration image has a second set of quiet regions that is at least partially non-overlapping with the first set of quiet regions. ### Claim 19 (depends on 14) The non-transitory computer-readable storage medium of claim 14, wherein the first configuration image has a first set of unused regions, and the second configuration image has a second set of unused regions that is at least partially non-overlapping with the first set of unused regions.