FPGA hardware-based secure computing method and apparatus

A non-transitory, computer-readable medium storing one or more instructions executable by a computer system to perform operations comprising:

• obtaining, at an FPGA hardware device, encrypted data of at least one participant of a plurality of participants of a secure computing system, wherein the FPGA hardware device stores a plurality of immutable first keys of a plurality of trusted managers, wherein the FPGA hardware device comprises an FPGA chip, and wherein the FPGA chip is configured based on running logic jointly determined by the plurality of trusted managers or by the plurality of participants of the secure computing system to prevent tampering of configuration of the FPGA chip;
• decrypting, at the FPGA hardware device and by using at least one dynamic working key of the at least one participant, the encrypted data of at least one participant to obtain plaintext data, wherein each dynamic working key of the at least one dynamic working key is obtained based on a corresponding immutable first key of the plurality of immutable first keys;
• performing, at the FPGA hardware device, computing based on the plaintext data to obtain a computing result;
• and
• outputting, at the FPGA hardware device, the computing result.

A computer-implemented system, comprising:

• one or more computers;
• and
• one or more computer memory devices interoperably coupled with the one or more computers and having tangible, non-transitory, machine-readable media storing one or more instructions that, when executed by the one or more computers, perform one or more operations comprising:
• obtaining, at an FPGA hardware device, encrypted data of at least one participant of a plurality of participants of a secure computing system, wherein the FPGA hardware device stores a plurality of immutable first keys of a plurality of trusted managers, wherein the FPGA hardware device comprises an FPGA chip, and wherein the FPGA chip is configured based on running logic jointly determined by the plurality of trusted managers or by the plurality of participants of the secure computing system to prevent tampering of configuration of the FPGA chip;
• decrypting, at the FPGA hardware device and by using at least one dynamic working key of the at least one participant, the encrypted data of at least one participant to obtain plaintext data, wherein each dynamic working key of the at least one dynamic working key is obtained based on a corresponding immutable first key of the plurality of immutable first keys;
• performing, at the FPGA hardware device, computing based on the plaintext data to obtain a computing result;
• and
• outputting, at the FPGA hardware device, the computing result.