Method of processing in memory (PIM) using memory device and memory device performing the same

A processing in memory (PIM) method using a memory device, the method comprising:

• determining each of p*r*q (i, k, j) multiplication values by multiplying a (i, k) multiplicand value included in a multiplicand matrix of p rows and r columns and a (k, j) multiplier value included in a multiplier matrix of r rows and q columns, with respect to all of i, k and j, where i is a natural number from 1 to p, k is a natural number from 1 to r, and j is a natural number from 1 to q;
• and
• determining each of p*q (i, j) component values included in a multiplication matrix of p rows and q columns corresponding to a multiplication of the multiplicand matrix and the multiplier matrix, by summing the r (i, k, j) multiplication values with respect to all of k, wherein:
• determining a p*r*q (i, k, j) multiplication value of the p*r*q (i, k, j) multiplication values comprises storing m*n multiplicand arrangement bits in m*n memory cells of the memory device by copying and arranging m multiplicand bits of the (i, k) multiplicand value where m and n are natural numbers greater than zero,
• storing m*n multiplier arrangement bits in m*n read-write unit circuits of the memory device corresponding to the m*n memory cells by copying and arranging n multiplier bits of the (k, j) multiplier value,
• selectively sensing fewer than all of the m*n multiplicand arrangement bits stored in the m*n memory cells based on the m*n multiplier arrangement bits stored in the m*n read-write unit circuits, and storing m*n multiplication bits in the m*n read-write unit circuits based on the selectively read m*n multiplicand arrangement bits, the m*n multiplication bits corresponding to bitwise multiplied values of the m*n multiplicand arrangement bits and the m*n multiplier arrangement bits, and
• determining the p*r*q (i, k, j) multiplication value of the (i, k) multiplicand value and the (k, j) multiplier value based on the m*n multiplication bits stored in the m*n read-write unit circuits, wherein the selectively sensing the m*n multiplicand arrangement bits and the storing the m*n multiplication bits in the m*n read-write unit circuits comprise:
• sensing multiplicand arrangement bits from among the m*n multiplicand arrangement bits that correspond to multiplier arrangement bits from among the m*n multiplier arrangement bits having a value of “1” from the m*n memory cells and replacing the multiplier arrangement bits having the value of “1” stored in the m*n read-write unit circuits with the sensed multiplicand arrangement bits;
• and
• maintaining multiplier arrangement bits from among the m*n multiplier arrangement bits having a value of “0” stored in the m*n read-write unit circuits regardless of values of multiplicand arrangement bits from among the m*n multiplicand arrangement bits that correspond to the multiplier arrangement bits having the value of “0”.

A memory device comprising:

• a data copy-arrangement circuit configured to generate multiplicand arrangement bits by copying and arranging multiplicand bits of multiplicand values included in a multiplicand matrix and to generate multiplier arrangement bits by copying and arranging multiplier bits of multiplier values included in a multiplier matrix;
• a memory cell array including memory cells connected to bitlines and configured to store the multiplicand arrangement bits;
• read-write unit circuits connected to the bitlines and configured to:
• store the multiplier arrangement bits,
• receive the multiplicand arrangement bits selectively sensed from fewer than all of the memory cells based on the multiplier arrangement bits stored in the read-write unit circuits, and
• store multiplication bits based on the multiplicand arrangement bits selectively sensed from the memory cells, the multiplication bits corresponding to bitwise multiplied values of the multiplicand arrangement bits and the multiplier arrangement bits;
• a control circuit configured to selectively sense the multiplicand arrangement bits by:
• sensing multiplicand arrangement bits from among the multiplicand arrangement bits that correspond to multiplier arrangement bits from among the multiplier arrangement bits having a value of “1” from the memory cells, and replacing the multiplier arrangement bits having the value of “1” stored in the read-write unit circuits with the sensed multiplicand arrangement bits, and
• maintaining multiplier arrangement bits from among the multiplier arrangement bits having a value of “0” stored in the read-write unit circuits regardless of values of multiplicand arrangement bits from among the multiplicand arrangement bits that correspond to the multiplier arrangement bits having the value of “0”;
• and
• an operation circuit configured to determine component values of a multiplication matrix corresponding to a multiplication of the multiplicand matrix and the multiplier matrix based on the multiplication bits stored in the read-write unit circuits.