# US 11,113,216 B2 · Dispatching interrupts in a multi-processor system based on power and performance factors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,216 B2 - Document ID: US11113216B2 - Status: Granted - Kind: B2 - Application number: 16/810,031 - Filed: 2020-03-05 - Published: 2020-09-24 - Granted: 2021-09-07 - Earliest claimed: 2019-03-20 - Assignees: Mediatek Inc. - Applicants: MediaTek Inc. - Inventors: Chia-Hao Hsu; Sen-Yu Cheng; Yan-Ting Chen; Po-Kai Chi - Web page: https://patentgrep.com/patent/US11113216B2 ## CPC - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F 1/3293: by switching to a less power-consuming processor, e.g. sub-CPU - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A multi-processor system handles interrupts using a power and performance status of each processor and a usage scenario of each processor. The power and performance status is indicated by factors that affect power consumption and processor performance. The system identifies one of the processors for handling an interrupt based on a weighted combination of the factors. Each factor is weighted based on a usage scenario for which the interrupt was generated. The system then dispatches the interrupt to the identified one of the processors. ## Claims ### Claim 1 A system for handling interrupts, comprising: a plurality of processors; an interrupt controller; and a plurality of interrupt-generating devices, wherein the interrupt controller is operative to: receive a power and performance status of each processor, the power and performance status indicated by a plurality of factors that affect power consumption and processor performance; receive a request for an interrupt from one of the interrupt-generating devices, the interrupt being generated in a usage scenario of the system; calculate a weighted combination of the factors for each processor, wherein each factor is weighted based on the usage scenario; identify one of the processors for handling the interrupt based on the weighted combination calculated for each processor; and dispatch the interrupt to the identified one of the processors. ### Claim 2 (depends on 1) The system of claim 1, wherein the factors for each processor include a measurement of demand imposed by current tasks on computing resources of the processor. ### Claim 3 (depends on 1) The system of claim 1, wherein the factors for each processor include a presence of a hard deadline imposed by current tasks on the processor. ### Claim 4 (depends on 1) The system of claim 1, wherein the factors for each processor include whether the processor is enabled to receive interrupts. ### Claim 5 (depends on 1) The system of claim 1, wherein the factors for each processor include a pending interrupt count of the processor. ### Claim 6 (depends on 1) The system of claim 1, wherein the factors for each processor include a power on/off state of the processor and a power on/off state of a cluster containing the processor. ### Claim 7 (depends on 1) The system of claim 1, wherein the factors for each processor include a power mode indicating an idle level of the processor. ### Claim 8 (depends on 1) The system of claim 1, wherein the factors for each processor include a state of energy efficiency of the processor with respect to an operating frequency of the processor. ### Claim 9 (depends on 1) The system of claim 1, wherein the interrupt controller is further operative to: in response to the usage scenario for which latency in response time of the interrupt dominates power consumption, assign higher weights to the factors that correspond to higher performance of the processor. ### Claim 10 (depends on 1) The system of claim 1, wherein the interrupt controller is further operative to: in response to the usage scenario for which power consumption dominates latency in response time of the interrupt, assign higher weights to the factors that correspond to lower power consumption of the processor. ### Claim 11 A method for handling an interrupt in a system including a plurality of processors, comprising: receiving a power and performance status of each processor, the power and performance status indicated by a plurality of factors that affect power consumption and processor performance; receiving a request for an interrupt from one of the interrupt-generating devices, the interrupt being generated in a usage scenario of the system; calculating a weighted combination of the factors for each processor, wherein each factor is weighted based on the usage scenario; identifying one of the processors for handling the interrupt based on the weighted combination of the factors; and dispatching the interrupt to the identified one of the processors. ### Claim 12 (depends on 11) The method of claim 11, wherein the factors for each processor include a measurement of demand imposed by current tasks on computing resources of the processor. ### Claim 13 (depends on 11) The method of claim 11, wherein the factors for each processor include a presence of a hard deadline imposed by current tasks on the processor. ### Claim 14 (depends on 11) The method of claim 11, wherein the factors for each processor include whether the processor is enabled to receive interrupts. ### Claim 15 (depends on 11) The method of claim 11, wherein the factors for each processor include a pending interrupt count of the processor. ### Claim 16 (depends on 11) The method of claim 11, wherein the factors for each processor include a power on/off state of the processor and a power on/off state of a cluster containing the processor. ### Claim 17 (depends on 11) The method of claim 11, wherein the factors for each processor include a power mode indicating an idle level of the processor. ### Claim 18 (depends on 11) The method of claim 11, wherein the factors for each processor include a state of energy efficiency of the processor with respect to an operating frequency of the processor. ### Claim 19 (depends on 11) The method of claim 11, further comprising: identifying the usage scenario as a process for which latency in response time of the interrupt dominates power consumption; and assigning higher weights to the factors that correspond to higher performance of the processor. ### Claim 20 (depends on 11) The method of claim 11, further comprising: identifying the usage scenario as a process for which power consumption dominates latency in response time of the interrupt; and assigning higher weights to the factors that correspond to lower power consumption of the processor.