# US 11,113,214 B2 · Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,214 B2 - Document ID: US11113214B2 - Status: Granted - Kind: B2 - Application number: 16/550,004 - Filed: 2019-08-23 - Published: 2021-02-25 - Granted: 2021-09-07 - Earliest claimed: 2019-08-23 - Assignees: Lenovo Enterprise Solutions (Singapore) Pte. Ltd. - Applicants: LENOVO Enterprise Solutions (Singapore) PTE. LTD. - Inventors: Jeffrey R. Hamilton; Sumanta K. Bahali; Peter R. Seidel; Brian E. Bigelow; Juan Q. Hernandez - Web page: https://patentgrep.com/patent/US11113214B2 ## CPC - G06F 13/1673: {using buffers} - G06F 3/061: {Improving I/O performance} - G06F 3/0613: {in relation to throughput} - G06F 3/0649: {Lifecycle management} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0673: {Single storage device} - G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays} - G06F 13/36: for access to common bus or bus system - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor. ## Claims ### Claim 1 An apparatus comprising: a high-speed fabric controller; a memory controller connected between a high-speed memory and a processor, the memory controller configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory; a data connection between the processor and the high-speed fabric controller; a high-speed data connection between the memory controller and the high-speed fabric controller; and a data connection between a tier of persistent data storage and the high-speed fabric controller, wherein the high-speed data connection between the memory controller and the high-speed fabric controller is separate from of the connection between the processor and the high-speed fabric controller, and wherein the high-speed fabric controller is configured to control data transfers between the tier of persistent data storage and the high-speed memory over the high-speed data connection and independent of the processor. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the high-speed fabric controller is configured to transfer data between the high-speed memory and the tier of persistent data storage without the data passing through the processor. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory over the high-speed data connection without involvement of the processor. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the high-speed data connection is a first high-speed data connection, the processor is a first processor, the memory controller is a first memory controller and the high-speed memory is a first high-speed memory and further comprising a second high-speed data connection between the high-speed fabric controller and a second memory controller connected between to a second high-speed memory and a second processor, the second memory controller configured to control second processor access to the second high-speed memory over a memory bus between the second processor and the second high-speed memory and wherein the high-speed fabric controller is configured to control data transfers between one or more of the first high-speed memory, the tier of persistent data storage and the second high-speed memory independent of the first processor and the second processor. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the high-speed fabric controller is configured to manage spare data capacity of the first high-speed memory and the second high-speed memory to share spare data capacity so that spare data capacity of the first high-speed memory and the second high-speed memory is less than spare data capacities of not sharing spare data capacity. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the tier of persistent data storage is a first tier of persistent data storage and further comprising one or more additional tiers of persistent data storage and wherein the high-speed fabric controller further comprises a data tiering aggregator that is configured to control data tiering between the high-speed memory, the first tier of persistent data storage and the one or more additional tiers of persistent data storage. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the data tiering aggregator is configured to manage data tiering independent of caching instructions from the processor. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the processor comprises a pre-fetch queue and requests data caching through the pre-fetch queue and the data tiering aggregator accesses the pre-fetch queue to fulfil caching requests from the processor. ### Claim 9 (depends on 6) The apparatus of claim 6, wherein the first tier of persistent data storage and the one or more additional tiers of persistent data storage are connected to the high-speed fabric controller over a high-speed data connection. ### Claim 10 (depends on 6) The apparatus of claim 6, wherein the high-speed memory and each tier of persistent data storage comprise a different data storage speed and the data tiering aggregator is configured to manage data tiering based on data storage speeds of the high-speed memory and each tier of persistent data storage. ### Claim 11 (depends on 6) The apparatus of claim 6, wherein the data tiering aggregator is configured to present data to the processor as a single data source without respect to a data tier of data storage controlled by the high-speed fabric controller. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein data connection between the memory controller and the processor comprises a parallel memory interface. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the memory controller is configured to respond to commands from the processor and the high-speed fabric controller. ### Claim 14 An apparatus comprising: a high-speed fabric controller comprising a data tiering aggregator; a memory controller connected between a high-speed memory and a processor, the memory controller configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory; a high-speed data connection between the memory controller and the high-speed fabric controller; a data connection between a first tier of persistent data storage and the high-speed fabric controller; and a data connection between each of one or more additional tiers of persistent data storage and the high-speed fabric controller; a data connection between the processor and the high-speed fabric controller, wherein the data tiering aggregator is configured to control data tiering between the high-speed memory, the first tier of persistent data storage and the one or more additional tiers of persistent data storage, and wherein the high-speed fabric controller is configured to control data transfers between the first tier of persistent data storage and the high-speed memory independent of the processor without the data passing through the processor. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the data tiering aggregator is configured to manage data tiering independent of caching instructions from the processor. ### Claim 16 (depends on 14) The apparatus of claim 14, wherein the high-speed memory and each tier of persistent data storage comprise a different data storage speed and the data tiering aggregator is configured to manage data tiering based on the data storage speeds of the high-speed memory and each tier of persistent data storage. ### Claim 17 (depends on 14) The apparatus of claim 14, wherein the data tiering aggregator is configured to present data to the processor as a single data source without respect to a data tier of data storage controlled by the high-speed fabric controller. ### Claim 18 A system comprising: a processor; a high-speed memory connected to the processor over a memory bus; a high-speed fabric controller; a memory controller connected between the high-speed memory and the processor, the memory controller configured to control processor access to the high-speed memory over the memory bus; a data connection between the processor and the high-speed fabric controller; a high-speed data connection between the memory controller and the high-speed fabric controller; and a data connection between each of one or more tiers of persistent data storage and the high-speed fabric controller, wherein the high-speed data connection between the memory controller and the high-speed fabric controller is separate from the connection between the processor and the high-speed fabric controller, and wherein the high-speed fabric controller is configured to control data transfers between the one or more tiers of persistent data storage and the high-speed memory independent of the processor. ### Claim 19 (depends on 18) The system of claim 18, wherein the high-speed data connection is a first high-speed data connection, the processor is a first processor, the memory controller is a first memory controller and the high-speed memory is a first high-speed memory, the system further comprising a second processor, a second high-speed memory, a second high-speed data connection between the high-speed fabric controller and a second memory controller connected between the second high-speed memory and the second processor, the second memory controller configured to control second processor access to the second high-speed memory over a parallel bus between the second processor and the second high-speed memory and wherein the high-speed fabric controller is configured to control data transfers between one or more of the first high-speed memory, the one or more tiers of persistent data storage and the second high-speed memory independent of the first processor and the second processor.