# US 11,113,213 B2 · Determining write commands for deletion in a host interface

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- Number: US 11,113,213 B2
- Document ID: US11113213B2
- Status: Granted
- Kind: B2
- Application number: 16/929,416
- Filed: 2020-07-15
- Published: 2021-07-01
- Granted: 2021-09-07
- Earliest claimed: 2019-12-30
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yue Chan
- Web page: https://patentgrep.com/patent/US11113213B2

## CPC

- G06F 13/1668: {Details of memory controller}
- G06F 11/1064: {in cache or content addressable memories}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An interface of a memory sub-system can determine that a particular write command received from a host has a same address as a subsequently received write command from the host. The interface can delete the particular write command if it is still in the interface or send a signal to delete the particular write command if the write command has already been provided from the interface.

## Claims

### Claim 1

A system comprising:
a memory device;
a processing device coupled to the memory device and configured to control cache memory for the memory device; and
an interface coupled to the processing device and configured to:
determine that a particular write command received from a host has a same address as a subsequently received write command from the host;
delete the particular write command in response to the particular write command not having been provided to the processing device; and
signal the processing device to delete the particular write command in response to the particular write command having been provided to the processing device;
wherein the processing device is configured to delete the particular write command in response to the signal.

### Claim 2 (depends on 1)

The system of claim 1, wherein the interface is further configured to provide the subsequently received write command to the processing device; and
wherein the processing device is configured to:
execute the subsequently received write command with respect to the cache memory; and
provide the subsequently received write command to a memory controller of the memory device.

### Claim 3 (depends on 2)

The system of claim 2, wherein the processing device is configured to provide the subsequently received write command to the memory controller of the memory device via the interface.

### Claim 4 (depends on 3)

The system of claim 3, wherein the interface is further configured to control timing of the provision of the subsequently received write command to the memory controller of the memory device based on an availability of the memory device to execute the subsequently received write command.

### Claim 5 (depends on 1)

The system of claim 1, wherein the interface is further configured to:
store, in command memory, a correlation between write commands and addresses thereof with respective identifications (IDs) of each of the write commands.

### Claim 6 (depends on 5)

The system of claim 5, wherein the interface is further configured to correlate with the respective IDs with an order in which the write commands were received by the interface.

### Claim 7 (depends on 6)

The system of claim 6, wherein the interface is further configured to determine that the particular write command was received prior to receipt of the subsequently received write command based on the order.

### Claim 8

A method comprising:
receiving a first write command from a host;
receiving a second write command from the host, wherein the first write command is received prior to receipt of the second write command;
determining whether the first write command and the second write command write to a same address;
responsive to a determination that the first write command and the second write command write to the same address, marking the first write command as erroneous utilizing error circuitry; and
deleting the first write command based on the marking of the error circuitry.

### Claim 9 (depends on 8)

The method of claim 8, further comprising processing, by a processing device, the second write command responsive to the second write command passing an error check.

### Claim 10 (depends on 8)

The method of claim 8, wherein marking the first write command for deletion further comprises utilizing the error circuitry to describe attributes of a stream of commands and a stream of data.

### Claim 11 (depends on 10)

The method of claim 10, wherein the stream of commands includes the first and the second write commands and the stream of data includes data corresponding to the first write command and data corresponding to the second write command.

### Claim 12 (depends on 8)

The method of claim 8, wherein marking the first write command further comprises marking the first write command as if there exists errors in data corresponding to the first write command.

### Claim 13

A system, comprising:
a memory device;
a processing device coupled to the memory device;
comparator circuitry coupled to the processing device and configured to:
access a first write command, a second write command, and a third write command received from a host;
determine that the first write command, the second write command, and the third write command write data to a same address of the memory device; and
mark the first write command and the second write command as erroneous utilizing error circuitry responsive to determining that the first write command, the second write command, and the third write command write data to the same address of the memory device and that the third write command is received after the first command and second write command;
wherein the processing device is configured to delete the first write command and the second write command in response to the first write command and the second write command being marked as erroneous.

### Claim 14 (depends on 13)

The system of claim 13, wherein the system further comprises an interface comprising the comparator circuitry, wherein the interface is configured to provide the first write command and the second write command to the processing device.

### Claim 15 (depends on 14)

The system of claim 14, wherein the interface is further configured to provide the third write command to the processing device for execution.

### Claim 16 (depends on 14)

The system of claim 14, wherein the interface further comprises:
the error circuitry; and
error memory wherein the error circuitry is further configured to store information in the error memory that identifies whether data corresponding to the first write command and the second write command passed an error correction check.

### Claim 17 (depends on 16)

The system of claim 16, wherein the interface is further configured to assign a first write ID to the first write command and a second write ID to the second write command.

### Claim 18 (depends on 17)

The system of claim 17, wherein the interface is further configured to store the first write ID and the second write ID in the error memory with the information stored by the error circuitry.

### Claim 19 (depends on 18)

The system of claim 18, wherein the interface is further configured to store an erroneous indication corresponding to the first write ID and the second write ID in the error memory with the information stored by the error circuitry to mark the first write command and the second write command.

### Claim 20 (depends on 17)

The system of claim 17, wherein the interface is further configured to release the first write ID and the second write ID responsive to a deletion of the first write command and the second write command by the processing device.