Memory device supporting rank-level parallelism and memory system including the same
AssigneesSK hynix Inc., Korea Advanced Institute of Science and Technology
InventorsWongyu Shin, Leesup Kim, Youngsuk Moon, Yongkee Kwon, Jaemin Jang
Life of this patent
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Abstract
A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.
Claims3
A memory system comprising one or more of memory modules coupled to a memory controller through a channel, each of the one or more of memory modules comprising a plurality of ranks, each of the plurality of ranks comprising a plurality of memory devices, wherein each of the plurality of memory devices comprises:
- a cell region;
- a row control circuit configured to control a row operation of the cell region;
- a column control circuit configured to control a column operation of the cell region;
- a command decoder configured to process a command provided from the memory controller and to control the row control circuit and the column control circuit;
- a data transceiver configured to transmit/receive data to/from the channel according to control of the command decoder;
- and
- an intermediate buffer configured to communicate with the column control circuit or the data transceiver according to a first plurality of control signals from the command decoder,
- wherein the memory device further comprises a path setting circuit including a first selector and a second selector, the first selector configured to couple the column control circuit to the data transceiver or the intermediate buffer, the second selector configured to couple the data transceiver to the column control circuit or the intermediate buffer, so that the path setting circuit sets a first data transmission path between the column control circuit and the intermediate buffer, a second data transmission path between the data transceiver and the intermediate buffer, or a third data transmission path between the column control circuit and the data transceiver, according to a second plurality of control signals from the command decoder.
Dependencies are inferred from the claim text.