# US 11,113,210 B2 · Memory device supporting rank-level parallelism and memory system including the same

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- Number: US 11,113,210 B2
- Document ID: US11113210B2
- Status: Granted
- Kind: B2
- Application number: 16/574,386
- Filed: 2019-09-18
- Published: 2020-02-27
- Granted: 2021-09-07
- Earliest claimed: 2016-11-01
- Assignees: SK hynix Inc.; Korea Advanced Institute of Science and Technology
- Applicants: SK hynix Inc.; Korea Advanced Institute of Science and Technology
- Inventors: Wongyu Shin; Leesup Kim; Youngsuk Moon; Yongkee Kwon; Jaemin Jang
- Web page: https://patentgrep.com/patent/US11113210B2

## CPC

- G06F 13/1647: {with interleaved bank access}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 12/0284: {Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163)}
- G06F 13/36: for access to common bus or bus system
- G06F 12/0607: {Interleaved addressing}
- G06F 2212/1024: Latency reduction
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A memory system may include: a memory controller; a plurality of ranks; and a rank shared bus configured to couple the memory controller and the plurality of ranks. Each of the plurality of ranks may include: a plurality of banks; a rank bus coupled to the plurality of banks and configured to selectively transmit data to the rank shared bus or an intermediate buffer and selectively receive data from the rank shared bus or the intermediate buffer; and an intermediate buffer configured to be selectively coupled to the rank bus or the rank shared bus, according to a first signal from the memory controller.

## Claims

### Claim 1

A memory device comprising:
a cell region;
a row control circuit configured to control a row operation of the cell region;
a column control circuit configured to control a column operation of the cell region;
a command decoder configured to process a command provided from a memory controller and to control the row control circuit and the column control circuit;
a data transmitter/receiver configured to transmit or receive data according to control of the command decoder;
an intermediate buffer configured to communicate with the column control circuit or the data transmitter/receiver according to a first plurality of control signals from the command decoder; and
a path setting circuit including a first selector and a second selector, the first selector configured to couple the column control circuit to the data transmitter/receiver or the intermediate buffer, the second selector configured to couple the data transmitter/receiver to the column control circuit or the intermediate buffer, so that the path setting circuit sets a first data transmission path between the column control circuit and the intermediate buffer, a second data transmission path between the data transmitter/receiver and the intermediate buffer, or a third data transmission path between the column control circuit and the data transmitter/receiver, according to a second plurality of control signals from the command decoder.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein when the command decoder processes a rank-level command, the command decoder causes the path setting circuit and the intermediate buffer to transmit data between the column control circuit and the intermediate buffer.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein when the command decoder processes a channel-level command, the command decoder causes the path setting circuit and the intermediate buffer to transmit data between the intermediate buffer and the data transmitter/receiver.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein the intermediate buffer comprises a plurality of entry circuits and an entry decoder, the entry decoder being configured to select one of the plurality of entry circuits according to the first plurality of control signals of the command decoder.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the cell region comprises a plurality of banks.