Translation invalidation in a translation cache serving an accelerator

A method of data processing in a coherent data processing system including a system memory, the method comprising:

• host attach logic communicating memory access requests with the coherent data processing system via a first communication interface;
• the host attach logic communicating, via a second communication interface, memory access requests with an accelerator unit including an effective address-based accelerator cache having multiple data entries for buffering copies of data from the system memory, wherein:
• all memory access requests of the accelerator unit requesting data in the system memory are received by the host attach logic;
• the accelerator cache tracks contents of the data entries based on effective addresses within an effective address space;
• and
• the host attach logic refrains from communicating real addresses with the accelerator unit;
• the host attach logic recording, in multiple directory entries of a real address-based directory inclusive of contents of the accelerator cache, which data from the system memory is accessed by the accelerator unit, wherein the recording includes assigning directory entries in the real address-based directory to track which data is stored in the accelerator cache based on real addresses utilized to identify storage locations in the system memory;
• and
• the host attach logic, based on receipt on the first communication interface of a translation entry invalidation request, issuing to the accelerator unit via the second communication interface an invalidation request that identifies a data entry among the multiple data entries in the effective address-based accelerator cache to be invalidated, wherein the invalidation request identifies the data entry in the effective address-based accelerator cache utilizing a host tag identifying a directory entry in the real address-based directory.

A design structure tangibly embodied in a storage device for designing, manufacturing, or testing an integrated circuit, the design structure comprising:

• host attach logic for a coherent data processing system including a system memory, the host attach logic including:
• a first communication interface for communicatively coupling the integrated circuit with the coherent data processing system;
• a second communication interface for communicatively coupling the integrated circuit with an accelerator unit such that all memory access requests of the accelerator unit requesting data in the system memory are received by the integrated circuit, wherein:
• the accelerator unit includes an effective address-based accelerator cache having multiple data entries for buffering copies of data from the system memory of the coherent data processing system;
• the accelerator cache tracks contents of the data entries based on effective addresses within an effective address space;
• and
• the integrated circuit is configured to refrain from communicating real addresses with the accelerator unit;
• a real address-based directory having multiple directory entries, wherein the real address-based directory is inclusive of contents of the accelerator cache, and wherein the real address-based directory assigns directory entries to track which data are stored in the accelerator cache based on real addresses utilized to identify storage locations in the system memory;
• and
• request logic configured to, based on receipt on the first communication interface of a translation entry invalidation request, issue to the accelerator unit via the second communication interface an invalidation request that identifies a data entry among the multiple data entries in the effective address-based accelerator cache to be invalidated, wherein the invalidation request identifies the data entry in the effective address-based accelerator cache utilizing a host tag identifying a directory entry in the real address-based directory.