Controller and method of operating the same
AssigneeSK hynix Inc.
InventorEu Joon Byun
Life of this patent
Estimating the term…
Abstract
Provided herein may be a controller and a method of operating the same. The controller for controlling an operation of a semiconductor memory device may include a request analyzer, a map cache controller, and a command generator. The request analyzer receives a first request from a host. The map cache controller generates a first mapping segment including a plurality of mapping entries and a flag bit based on the first request, and sets a value of the flag bit depending on whether data corresponding to the first mapping segment is random data or sequential data. The command generator generates a program command for programming the mapping segment.
Claims14
A controller for controlling an operation of a semiconductor memory device, the controller comprising:
- a map cache configured to store a first mapping segment including a plurality of mapping entries and a flag bit;
- and
- a map cache controller configured to:
- set a value of the flag bit depending on whether data corresponding to the first mapping segment is random data or sequential data;
- receive a second mapping segment from the semiconductor memory device when the second mapping segment corresponding to a read request from a host is in a cache miss in the map cache;
- and
- store the second mapping segment in one of a random map cache and a sequential map cache based on a value of a flag bit included in the second mapping segment.
A method of operating a controller for controlling a semiconductor memory device, the method comprising:
- receiving a read request of data from a host;
- providing the semiconductor memory device with;
- a read command for reading a mapping segment corresponding to the data when the mapping segment is in a cache miss in a map cache;
- receiving the mapping segment including a flag bit from the semiconductor memory device;
- and
- storing the mapping segment in one of a random map cache and a sequential map cache included in the map cache based on a value of the flag bit, wherein, the value of the flag bit is determined based on whether the data corresponding to the mapping segment is sequential data or random data.
Dependencies are inferred from the claim text.