Timed data transfer between a host system and a memory sub-system
AssigneeMicron Technology, Inc.
InventorSanjay Subbarao
Life of this patent
Estimating the term…
Loading patent…
AssigneeMicron Technology, Inc.
InventorSanjay Subbarao
Estimating the term…
A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.
A method, comprising:
A memory sub-system, comprising:
A non-transitory computer storage medium storing instructions which, when executed in a memory sub-system, causes the memory sub-system to perform a method, the method comprising:
Dependencies are inferred from the claim text.