# US 11,113,196 B2 · Shared buffered memory routing

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- Number: US 11,113,196 B2
- Document ID: US11113196B2
- Status: Granted
- Kind: B2
- Application number: 16/140,482
- Filed: 2018-09-24
- Published: 2019-04-11
- Granted: 2021-09-07
- Earliest claimed: 2015-03-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Debendra Das Sharma; Michelle C. Jen; Brian S. Morris
- Web page: https://patentgrep.com/patent/US11113196B2

## CPC

- G06F 12/084: with a shared cache
- G06F 3/061: {Improving I/O performance}
- G06F 3/0635: {by changing the path, e.g. traffic rerouting, path reconfiguration}
- G06F 3/0673: {Single storage device}
- G06F 12/0806: Multiuser, multiprocessor or multiprocessing cache systems
- G06F 12/0808: with cache invalidating means (G06F12/0815 takes precedence)
- G06F 13/1673: {using buffers}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G06F 2212/1016: Performance improvement
- G06F 2212/60: Details of cache memory
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

## Claims

### Claim 1

An apparatus comprising:
a first device comprising at least a portion of an interconnect fabric, a first shared memory controller to control access to first shared memory, and a first plurality of processor nodes, wherein the first device further comprises an interface to receive a data request from a second device over a data link, the interface comprises physical layer circuitry to implement a physical layer for the data link according to a physical layer protocol, and the interface further comprises first link layer circuitry to implement a first link layer protocol and second link layer circuitry to implement a different second link layer protocol,
wherein the data link comprises a plurality of lanes, the data link supports multiplexing of data of the different first and second link layer protocols over the same physical layer of the data link, the first shared memory is not directly connected to the processor nodes, and the second device comprises a second shared memory controller to couple and control access to second shared memory, and a second plurality of processor nodes,
wherein the data request comprises link layer data, the data request is addressed to be routed to the first memory controller through the interconnect fabric from the second device, and the first memory controller is to handle the data request, wherein the data request comprises a node identifier to identify a particular processor node of the second plurality of processor nodes as a source of the data request, and the data request further comprises an address to identify a portion of the first shared memory associated with the data request.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the first and second shared memory comprise shared memory of a platform comprising the first device and the second device.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the first shared memory comprises dynamic random-access memory (DRAM).

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the first shared memory comprises dual in-line memory module (DIMM) memory.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first memory controller is coupled directly to the first shared memory by a double data rate (DDR) connection.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the data link comprises a physical layer based at least in part on a Peripheral Component Interconnect Express (PCIe)-based physical layer.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the interface comprises a serializer/deserializer (SerDes).

### Claim 8 (depends on 1)

The apparatus of claim 1, wherein the data link comprises a multilane link.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the multilane link comprises at least eight lanes.

### Claim 10 (depends on 1)

The apparatus of claim 1, wherein the data request comprises one of a read request or write request of the portion of the first shared memory.

### Claim 11

A system comprising:
a first die comprising at least a portion of an interconnect fabric, a first memory controller to couple to first shared memory, and a first plurality of processor nodes, wherein the first plurality of processor nodes are not directly connected; and
a second die, coupled to the first die by a data link, wherein the second die comprises a second memory controller to couple to second shared memory, and a second plurality of processor nodes,
wherein the data link comprises a plurality of lanes, the data link supports multiplexing of data of different link layer protocols over a common physical layer of the data link, a particular one of the first plurality of processor nodes is to send a memory request, the memory request is to be routed to the second memory controller, and the second memory controller is to handle the memory request, wherein the memory request comprises link layer data comprising a node identifier to identify the particular processor node and an address to identify a portion of the second shared memory.

### Claim 12 (depends on 11)

The system of claim 11, wherein the second die implements at least a portion of the interconnect fabric.

### Claim 13 (depends on 11)

The system of claim 11, wherein the system comprises a rack server system.

### Claim 14 (depends on 11)

The system of claim 11, wherein the first and second memory comprise shared memory of the system.

### Claim 15 (depends on 11)

The system of claim 11, wherein the first and second memory each respectively comprise dynamic random-access memory (DRAM).

### Claim 16 (depends on 15)

The system of claim 15, wherein the first and second memory each respectively comprise dual in-line memory module (DIMM) memory.