Generating a debugging network for a synchronous digital circuit during compilation of program source code

A computer for generating and debugging synchronous digital circuits, comprising:

• a central processing unit (CPU);
• and
• at least one computer storage medium storing program source code in a multi-threaded imperative programming language, and a plurality of instructions, which when executed by the CPU, cause the processor to:
• compile the program source code in the multi-threaded imperative programming language into a circuit description for a synchronous digital circuit, wherein the circuit description comprises data defining a debugging network connected to a plurality of pipelines;
• automatically generate a debugging request to query the plurality of pipelines for state information by way of the debugging network;
• and
• provide the debugging request to the debugging network to query the plurality of pipelines for state information, wherein the debugging request is provided automatically in response to determining that a predetermined time period has elapsed.

A synchronous digital circuit, comprising:

• a plurality of pipelines;
• queues connecting the plurality of pipelines;
• and
• a debugging network configured for connection to a central processing unit (CPU),
• wherein the CPU automatically generates a debugging request to query the plurality of pipelines for state information by way of the debugging network,
• wherein the synchronous digital circuit is automatically generated based upon a circuit description generated from program source code in a multi-threaded imperative programming language, and
• wherein the debugging request is provided to the debugging network by the CPU to query the plurality of pipelines for state information, wherein the debugging request is provided automatically in response to determining that a predetermined time period has elapsed.