US 11,113,162 B2 · Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface

Abstract

Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface are disclosed. An example apparatus includes a first stack that includes a plurality of first dies stacked with one another, the first dies include a plurality of first channels, at least one of which is designated as a first defective channel, and further includes a second stack stacked with the first stack and including a plurality of second dies stacked with one another, the second dies including a plurality of second channels, at least one of which is designated as a second defective channel. A control circuit is configured, responsive to a command for accessing the first defective channel, to access one of the plurality of second channels in place of accessing the first defective channel, wherein the one of the plurality of second channels corresponds to the first defective channel and is not designated as the second defective channel.

Claims20

Dependent claims

An apparatus comprising:

a first stack comprising a plurality of first dies stacked with one another, the plurality of first dies comprising a plurality of first channels;
a second stack comprising a plurality of second dies stacked with one another, the second stack being stacked with the first stack, the plurality of second dies comprising a plurality of second channels, wherein each of the plurality of second channels corresponds to a respective channel in the plurality of first channels in the plurality of first dies;
and
a control circuit configured to, responsive to a command for accessing a channel in the plurality of first channels:
access a channel in the plurality of second channels corresponding to the channel in the plurality of first channels in place of accessing the channel if the channel is defective;
and
access the channel in the plurality of first channels, otherwise.

4 more elements

An apparatus, comprising:

an interface die coupled to a first plurality of memory devices and a second plurality of memory devices, each of the first plurality of memory devices corresponding to a memory of the second plurality of memory devices, the interface die is configured to access respective memory of the first and second plurality of memory devices responsive to memory commands, the interface die including:
a storage circuit configured to store information that indicates operability of respective memory of the first and second plurality of memory devices;
a repair circuit configured to receive the information stored in the storage circuit and to provide a select signal to activate a memory of the first plurality of memory devices to be accessed responsive to a memory command to access a memory of the second plurality of memory devices when the information indicates that the memory of the second plurality of memory devices is inoperable.

Dependencies are inferred from the claim text.

Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface

Life of this patent

Apparatuses and methods for repairing memory devices including a plurality of memory die and an interface

Life of this patent

Abstract

Claims20