# US 11,113,108 B1 · Managing programmable logic-based processing unit allocation on a parallel data processing platform > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,108 B1 - Document ID: US11113108B1 - Status: Granted - Kind: B1 - Application number: 17/212,903 - Filed: 2021-03-25 - Published: 2021-09-30 - Granted: 2021-09-07 - Earliest claimed: 2011-11-04 - Assignees: ThroughPuter, Inc. - Applicants: ThroughPuter, Inc. - Inventors: Mark Henrik Sandstrom - Web page: https://patentgrep.com/patent/US11113108B1 ## CPC - G06F 9/5011: {the resources being hardware resources other than CPUs, Servers and Terminals} - G06F 9/46: Multiprogramming arrangements - G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues} - G06F 9/505: {considering the load} - G06F 9/5016: {the resource being the memory} - G06F 9/5027: {the resource being a machine, e.g. CPUs, Servers, Terminals} - G06F 9/5038: {considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups)} - G06F 9/54: Interprogram communication - G06F 9/544: {Buffers; Shared memory; Pipes} - G06F 9/546: {Message passing systems or structures, e.g. queues} - G06F 15/17337: {Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004)} - H04L 49/15: Interconnection of switching modules - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Systems and methods provide an extensible, multi-stage, realtime application program processing load adaptive, manycore data processing architecture shared dynamically among instances of parallelized and pipelined application software programs, according to processing load variations of said programs and their tasks and instances, as well as contractual policies. The invented techniques provide, at the same time, both application software development productivity, through presenting for software a simple, virtual static view of the actually dynamically allocated and assigned processing hardware resources, together with high program runtime performance, through scalable pipelined and parallelized program execution with minimized overhead, as well as high resource efficiency, through adaptively optimized processing resource allocation. ## Claims ### Claim 1 A method on a parallel data processing platform comprising a plurality of programmable logic-based processing units for accelerating a service comprising at least a first program and a second program, different than the first program, the method comprising: forming a first set of inter-task communication paths connecting a first set of programmable logic-based processing units of the plurality of programmable logic-based processing units into a first multi-stage program instance, wherein the first multi-stage program instance is configured to accelerate the first program, and wherein the first set of programmable logic-based processing units are interconnected using reconfigurable cross-connects; forming a second set of inter-task communication paths connecting a second set of programmable logic-based processing units of the plurality of programmable logic-based processing units to a second multi-stage program instance, wherein the second multi-stage program instance is configured to accelerate the second program, and wherein the second set of programmable logic-based processing units are interconnected using reconfigurable cross-connects; in response to a first increased demand for the first multi-stage program instance determined by monitoring a first characteristic corresponding to the first set of programmable logic-based processing units, based on an adaptive optimized resource allocation policy, adding at least one more programmable logic-based processing unit to the first set of programmable logic-based processing units from the plurality of programmable logic-based processing units; and in response to a second increased demand for the second multi-stage program instance determined by monitoring a second characteristic different from the first characteristic, corresponding to the second set of programmable logic-based processing units, based on the adaptive optimized resource allocation policy, adding at least one more programmable logic-based processing unit to the second set of programmable logic-based processing units from the plurality of programmable logic-based processing units. ### Claim 2 (depends on 1) The method of claim 1, wherein the allocation policy relates to balancing load among programmable logic-based processing units. ### Claim 3 (depends on 1) The method of claim 1, wherein each of the first set of programmable logic-based processing units comprises a field programmable gate array (FPGA). ### Claim 4 (depends on 1) The method of claim 1, wherein each of the second set of programmable logic-based processing units comprises a field programmable gate array (FPGA). ### Claim 5 (depends on 1) The method of claim 1, wherein the first characteristic or the second characteristic is load or utilization. ### Claim 6 A non-transitory computer program product comprising instructions configured to perform a method parallel data processing platform comprising a plurality of programmable logic-based processing units for accelerating a service comprising at least a first program and a second program different than the first program, the method comprising: forming a first set of inter-task communication paths connecting a first set of programmable logic-based processing units of the plurality of programmable logic-based processing units into a first multi-stage program instance, wherein the first multi-stage program instance is configured to accelerate the first program, and wherein the first set of programmable logic-based processing units are interconnected using reconfigurable cross-connects; forming a second set of inter-task communication paths connecting a second set of programmable logic-based processing units of the plurality of programmable logic-based processing units to a second multi-stage program instance, wherein the second multi-stage program instance is configured to accelerate the second program, and wherein the second set of programmable logic-based processing units are interconnected using reconfigurable cross-connects; in response to a first increased demand for the first multi-stage program instance determined by monitoring a first characteristic corresponding to the first set of programmable logic-based processing units, based on an adaptive optimized resource allocation policy, adding at least one more programmable logic-based processing unit to the first set of programmable logic-based processing units from the plurality of programmable logic-based processing units; and in response to a second increased demand for the second multi-stage program instance determined by monitoring a second characteristic different from the first characteristic, corresponding to the second set of programmable logic-based processing units, based on the adaptive optimized resource allocation policy, adding at least one more programmable logic-based processing unit to the second set of programmable logic-based processing units from the plurality of programmable logic-based processing units. ### Claim 7 (depends on 6) The non-transitory computer program product of claim 6, wherein the allocation policy relates to balancing load among programmable logic-based processing units. ### Claim 8 (depends on 6) The non-transitory computer program product of claim 6, wherein each of the first set of programmable logic-based processing units comprises a field programmable gate array (FPGA). ### Claim 9 (depends on 6) The non-transitory computer program product of claim 6, wherein each of the second set of programmable logic-based processing units comprises a field programmable gate array (FPGA). ### Claim 10 (depends on 6) The non-transitory computer program product of claim 6, wherein the first characteristic or the second characteristic is load or utilization. ### Claim 11 A system comprising: a plurality of programmable logic-based processing units, each processing unit being configurable in at least a first configuration and a second configuration, different from the first configuration; a first set of inter-task communication paths connecting a first set of programmable logic-based processing units of the plurality of programmable logic-based processing units into a first multi-stage program instance, wherein the first-multi-stage program instance is configured to accelerate the first program, and wherein the first set of programmable logic-based processing units are interconnected using reconfigurable cross-connects; a second set of inter-task communication paths connecting a second set of programmable logic-based processing units of the plurality of programmable logic-based processing units to a second multi-stage program instance configured to execute the second program, and wherein the second set of programmable logic-based processing units are interconnected using reconfigurable cross-connects; and a hardware logic and/or one or more processors executing computer-executable instructions configured to (1) add, based on an allocation policy, in response to a first increased demand for the first multi-stage program instance determined by monitoring a first characteristic corresponding to the first set of programmable logic-based processing units, at least one more programmable logic-based processing unit to the first set of programmable logic-based processing units from the plurality of programmable logic-based processing units, and (2) add, based on the allocation policy, in response to a second increased demand for the second multi-stage program instance determined by monitoring a second characteristic, different from the first characteristic, corresponding to the second set of programmable logic-based processing units, at least one more programmable logic-based processing unit to the second set of programmable logic-based processing units from the plurality of programmable logic-based processing units. ### Claim 12 (depends on 11) The system of claim 11, wherein the allocation policy relates to balancing load among programmable logic-based processing units. ### Claim 13 (depends on 11) The system of claim 11, wherein each of the first set of programmable logic-based processing units comprises a field programmable gate array (FPGA). ### Claim 14 (depends on 11) The system of claim 11, wherein each of the second set of programmable logic-based processing units comprises a field programmable gate array (FPGA). ### Claim 15 (depends on 11) The system of claim 11, wherein the first characteristic or the second characteristic is load or utilization.