# US 11,113,102 B2 · Data storage device

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- Number: US 11,113,102 B2
- Document ID: US11113102B2
- Status: Granted
- Kind: B2
- Application number: 16/416,327
- Filed: 2019-05-20
- Published: 2020-02-27
- Granted: 2021-09-07
- Earliest claimed: 2018-08-22
- Assignees: Silicon Motion, Inc.
- Applicants: Silicon Motion, Inc.
- Inventors: Jyun-Han Wu
- Web page: https://patentgrep.com/patent/US11113102B2

## CPC

- G06F 3/061: {Improving I/O performance}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 9/3877: {using a secondary processor, e.g. coprocessor (peripheral processor G06F13/12)}
- G06F 9/544: {Buffers; Shared memory; Pipes}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A data storage device with a controller using a central processing unit (CPU) in a multi-stage architecture is shown. The processing systems of the different stages communicate with each other. In a first processing system, a command controller is provided to implement the first processing system as a transmitting end, and the command controller includes a plurality of command queues. When a first command is queued in a first command queue for transmission, a first processor of the first processing system fills a second command into a second command queue for transmission.

## Claims

### Claim 1

A data storage device, comprising:
a non-volatile memory; and
a controller, operating the non-volatile memory and including a central processing unit,
wherein:
the central processing unit has a multi-stage architecture, and different processing systems of the different stages communicate with each other;
in a first processing system within the central processing unit of the controller of the data storage device, a command controller is provided to implement the first processing system as a transmitting end, and the command controller includes a plurality of command queues;
when a first command is queued in a first command queue within the command controller for transmission, a first processor of the first processing system fills a second command into a second command queue within the command controller for transmission;
after transferring the first command queued in the first command queue to a receiving end, implemented by another processing system in another stage, through a communication interface, the command controller waits for an acknowledgement signal from the receiving end to confirm the transfer of the first command;
after receiving the acknowledgement signal, the command controller uses the communication interface to transfer the second command queued in the second command queue to output the second command from the first processing system without holding the second command to wait for a complete execution of the first command; and
the communication interface is an Advanced Extensible Interface.

### Claim 2 (depends on 1)

The data storage device as claimed in claim 1, wherein:
the first command queue corresponds to a first storage device, and the first command queued in the first command queue and transmitted from the first processing system regards the first storage device as destination; and
the second command queue corresponds to a second storage device, and the second command queued in the second command queue and transmitted from the first processing system regards the second storage device as destination.

### Claim 3 (depends on 2)

The data storage device as claimed in claim 2, further comprising:
a second processing system within the central processing unit of the controller of the data storage device, having a second processor as well as the first storage device;
the first command transferred to the first storage device is accessed and executed by the second processor;
a third processing system within the central processing unit of the controller of the data storage device, having a third processor as well as the second storage device; and
the second command transferred to the second storage device is accessed and executed by the third processor.

### Claim 4 (depends on 1)

The data storage device as claimed in claim 1, wherein:
commands queued in the command queues of the command controller are alternately transferred through the communication interface in a Round Robin scheduling manner.

### Claim 5 (depends on 1)

The data storage device as claimed in claim 1, wherein:
the command controller includes a Round Robin scheduling controller; and
each of the command queues of the command controller has a Round Robin scheduling queue for queuing commands; and
the commands queued in each Round Robin scheduling queue are accessed by the Round Robin scheduling controller to be transferred through the communication interface.

### Claim 6 (depends on 1)

The data storage device as claimed in claim 1, wherein:
the command queues correspond to different command attributions and are provided to separate the commands of the different command attributions.

### Claim 7 (depends on 6)

The data storage device as claimed in claim 6, wherein:
each of the command queues includes a first-in first-out buffer; and
commands of the same command attribution are queued in the same first-in first-out buffer.

### Claim 8 (depends on 6)

The data storage device as claimed in claim 6, wherein:
each command is pushed into the corresponding command queue without writing information regarding command attribution to the corresponding command queue.