# US 11,113,099 B2 · Method and apparatus for protecting a program counter structure of a processor system and for monitoring the handling of an interrupt request > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,099 B2 - Document ID: US11113099B2 - Status: Granted - Kind: B2 - Application number: 15/738,423 - Filed: 2016-05-04 - Published: 2018-06-28 - Granted: 2021-09-07 - Earliest claimed: 2015-06-22 - Assignees: Robert Bosch GmbH - Applicants: Robert Bosch GmbH - Inventors: Alexander Emperle; Jo Pletinckx; Jan Scheuing - Web page: https://patentgrep.com/patent/US11113099B2 ## CPC - G06F 9/4831: {with variable priority} - G06F 9/321: {Program or instruction counter, e.g. incrementing} - G06F 9/327: {for interrupts} - G06F 9/4812: {by interrupt, e.g. masked} - G06F 11/004: {Error avoidance (G06F11/07 and subgroups take precedence)} - G06F 11/0715: {in a system implementing multitasking (multitasking per se G06F9/46)} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/1608: {Error detection by comparing the output signals of redundant hardware (G06F11/1629, G06F11/1666 take precedence; error detection or correction in information storage based on relative movement between record carrier and transducer G11B20/18; checking static stores for correct operation G11C29/00; for logic circuits H03K19/003, H03K19/007; for pulse counters or frequency dividers H03K21/40)} - G06F 11/1637: {using additional compare functionality in one or some but not all of the redundant processing components} - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 13/24: using interrupt (G06F13/32 takes precedence) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor system comprises at least a program counter structure, an interrupt control device, a memory, and an apparatus. The interrupt control device is configured to respond to an interrupt request by providing the program counter structure with an address associated with the interrupt request. The program counter structure is configured to output the address to the memory via a memory interface. The apparatus is configured to protect the program counter structure in case of an interrupt request, the apparatus includes an interface, a comparing device, and an outputting device. ## Claims ### Claim 1 A method for protecting a program counter structure of a processor system in case of an interrupt request, the processor system comprising at least the program counter structure, an interrupt control device, and a memory, the method comprising: responding to the interrupt request with the interrupt control device by providing the program counter structure with an address associated with the interrupt request, the address being one of an interrupt vector and a starting address of an interrupt routine associated with the interrupt request; outputting the address with the program counter structure via a memory interface with respect to the memory; reading in the address from the memory interface; comparing the address with a target address assigned to the interrupt request, in order to obtain a comparison result; and providing a match signal based on the comparison result. ### Claim 2 (depends on 1) The method as claimed in claim 1, comprising: signaling a successful beginning of a processing of the interrupt request by using the match signal. ### Claim 3 (depends on 1) The method as claimed in claim 1, further comprising: providing the memory interface with a subsequent address with the program counter structure, the subsequent address logically following the address; reading-in the subsequent address; and comparing the subsequent address with a subsequent target address that logically follows the target address, in order to obtain the comparison result. ### Claim 4 (depends on 1) The method as claimed in claim 1, further comprising: monitoring a handling of the interrupt request by using the match signal. ### Claim 5 (depends on 1) The method as claimed in claim 1, wherein a computer program is configured to perform the method. ### Claim 6 (depends on 5) The method as claimed in claim 5, wherein the computer program is stored on a machine readable storage medium. ### Claim 7 An apparatus for protecting a program counter structure of a processor system in case of an interrupt request, the processor system comprising at least the program counter structure, an interrupt control device, and a memory, the interrupt control device configured to respond to the interrupt request by providing the program counter structure with an address associated with the interrupt request, the address being one of an interrupt vector and a starting address of the interrupt routine associated with the interrupt request, and the program counter structure configured to output the address to a memory interface with respect to the memory, the apparatus comprising: an interface configured to read in the address from the memory interface; a comparing device configured to compare the address with a target address assigned to the interrupt request, in order to obtain a comparison result; and an outputting device configured to provide a match signal based on the comparison result. ### Claim 8 A processor system comprising: at least an interrupt control device; a program counter structure; a memory; and an apparatus configured to protect the program counter structure in case of an interrupt request, the apparatus including an interface, a comparing device, and an outputting device, wherein the interrupt control device is configured to respond to the interrupt request by providing the program counter structure with an address associated with the interrupt request, the address being one of an interrupt vector and a starting address of the interrupt routine associated with the interrupt request, wherein the program counter structure is configured to output the address to a memory interface with respect to the memory, wherein the interface of the apparatus is configured to read in the address from the memory interface, wherein the comparing device is configured to compare the address with a target address assigned to the interrupt request, in order to obtain a comparison result, and wherein the outputting device is configured to provide a match signal by using a comparison result of the comparison. ### Claim 9 (depends on 8) The processor system as claimed in claim 8, wherein the program counter structure is part of a processor core, which along with the program counter structure comprises at least an electronic arithmetic and logic unit. ### Claim 10 (depends on 9) The processor system as claimed in claim 9, wherein the processor system is realized as an integrated circuit.