# US 11,113,073 B2 · Dual mode hardware reset > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,073 B2 - Document ID: US11113073B2 - Status: Granted - Kind: B2 - Application number: 16/425,127 - Filed: 2019-05-29 - Published: 2020-12-03 - Granted: 2021-09-07 - Earliest claimed: 2019-05-29 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Greg A. Blodgett - Web page: https://patentgrep.com/patent/US11113073B2 ## CPC - G06F 9/4418: {Suspend and resume; Hibernate and awake} - G06F 1/24: Resetting means - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/3296: by lowering the supply or operating voltage - G06F 3/0625: {Power saving in storage systems} - G06F 3/0634: {by changing the state or mode of one or more devices} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G06F 13/1668: {Details of memory controller} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Systems and methods are disclosed, including selectively providing one of a first reset or a second reset to transition to a storage system from a low power mode to an operational power mode in response to a hardware reset signal and a value of a control bit on the storage system. ## Claims ### Claim 1 A host system comprising: a host device comprising a host processor; a storage system comprising at least one non-volatile memory device, control circuitry coupled to the non-volatile memory device, and a storage register to store at least one control bit; and a communication interface between the host device and the storage system; and a reset interface between the host device and the storage system, wherein the host device is configured to control a power mode of the storage system, the power mode comprising an operational mode and a low power mode in which the communication interface is disabled, wherein, in the low power mode, the control circuitry is configured to provide one of a first reset or a second reset to transition to the storage system from the low power mode to the operational power mode in response to a reset signal from the host device on the reset interface and a value of the at least one control bit, wherein, in the operational power mode, the host processor is configured to control the value of the at least one control bit, and wherein, in the low power mode, the control circuitry is configured to control the value of the at least one control bit. ### Claim 2 (depends on 1) The host system of claim 1, wherein the first reset has a first latency and a first power requirement, wherein the second reset has a second latency and a second power requirement, and wherein the second latency is less than the first latency and the first power requirement is lower than the second power requirement. ### Claim 3 (depends on 1) The host system of claim 1, comprising: a bidirectional communication interface, wherein the host processor is configured to disable the bidirectional communication interface in the low power mode. ### Claim 4 (depends on 3) The host system of claim 3, wherein the host processor is configured to enable the bidirectional communication interface in the operational power mode. ### Claim 5 (depends on 1) The host system of claim 1, wherein the operational power mode is a normal power mode and the low power mode is a deep sleep mode, wherein the first reset is a normal reset including re-initialization the control circuitry, the group of non-volatile memory cells, and wherein the second reset is a modified reset including a limited re-initialization of the storage system to decrease a time of the transition from the low power mode to the operational power mode. ### Claim 6 (depends on 1) The host system of claim 1, wherein the host device includes a USF host, wherein the storage system comprises UFS device, wherein the at least one control bit comprises multiple control bits indicative of multiple different resets, and wherein, in the low power mode, the control circuitry is configured to provide one of the multiple resets in response to the hardware reset signal and the values of the multiple control bits. ### Claim 7 (depends on 1) The host system of claim 1, wherein, in the low power mode, the control circuitry is configured to: provide the first reset to transition the storage system from the low power mode to the operational power mode in response to the reset signal from the host device on the reset interface and the at least one control bit having a first value; and provide the second reset to transition the storage system from the low power mode to the operational power mode in response to the reset signal from the host device on the reset interface and the at least one control bit having a second value. ### Claim 8 A system comprising: a storage system comprising a group of non-volatile memory cells, control circuitry coupled to the group of non-volatile memory cells, and at least one control bit, wherein, in an operational power mode of the storage system, the control circuitry is configured to communicate with a host device through a bidirectional communication interface, wherein, in a low power mode of the storage system, the control circuitry is configured to provide one of a first reset or a second reset to transition to the storage system from the low power mode to the operational power mode in response to a hardware reset signal and a value of the at least one control bit, wherein the value of the at least one control bit is controlled by the host device in the operational power mode of the storage system and by the storage system in the low power mode of the storage system. ### Claim 9 (depends on 8) The system of claim 8, wherein, in the operational power mode of the storage system, the at least one control bit is controlled by the host device through the bidirectional communication interface, wherein the storage system is configured to store a value on the at least one control bit in response to a command from the host device, wherein, in the low power mode of the storage system, the bidirectional communication interface is disabled, and the at least one control bit is controlled by the storage system, and wherein the low power mode is a lower-power mode than the operational power mode. ### Claim 10 (depends on 8) The system of claim 8, wherein the first reset has a first latency and a first power requirement, wherein the second reset has a second latency and a second power requirement, and wherein the second latency is less than the first latency and the first power requirement is lower than the second power requirement. ### Claim 11 (depends on 8) The system of claim 8, wherein the operational power mode is a normal power mode and the low power mode is a deep sleep mode, wherein the first reset is a normal reset including re-initialization of the control circuitry, the group of non-volatile memory cells, and wherein the second reset is a modified reset including a limited re-initialization of the storage system to decrease a time of the transition from the low power mode to the operational power mode. ### Claim 12 (depends on 8) The system of claim 8, wherein the storage system comprises UFS device, wherein the at least one control bit comprises multiple control bits indicative of multiple, different resets, and wherein, in the low power mode, the control circuitry is configured to provide one of the multiple resets in response to the hardware reset signal and the values of the multiple control bits. ### Claim 13 A method implemented by control circuitry of a storage system, the method comprising: receiving, in a low power mode of the storage system, a hardware reset signal from a host device; and providing one of a first reset or a second reset to transition to the storage system from the low power mode to an operational power mode in response to the received hardware reset signal and a value of at least one control bit on the storage system, wherein the value of the at least one control bit is controlled by the host device in the operational power mode and the storage system in the low power mode. ### Claim 14 (depends on 13) The method of claim 13, wherein the low power mode is a lower-power mode than the operational power mode. ### Claim 15 (depends on 13) The method of claim 13, wherein the first reset has a first latency and a first power requirement, wherein the second reset has a second latency and a second power requirement, and wherein the second latency is less than the first latency and the first power requirement is lower than the second power requirement. ### Claim 16 (depends on 13) The method of claim 13, wherein the operational power mode is a normal power mode and the low power mode is a deep sleep mode, and wherein the first reset is a normal reset including re-initialization the control circuitry, the group of non-volatile memory cells, and wherein the second reset is a modified reset including a limited re-initialization of the storage system to decrease a time of the transition from the low power mode to the operational power mode. ### Claim 17 (depends on 13) The method of claim 13, wherein the storage system comprises a UFS device, wherein the at least one control bit comprises multiple control bits indicative of multiple different resets, and wherein, in the low power mode, the control circuitry is configured to provide one of the multiple resets in response to the hardware reset signal and the values of the multiple control bits. ### Claim 18 A non-transitory machine-readable medium, storing instructions, which when executed by a storage system, cause the storage system to perform operations comprising: receiving, in a low power mode of the storage system, a hardware reset signal from a host device; and providing one of a first reset or a second reset to transition to the storage system from the low power mode to an operational power mode in response to the received hardware reset signal and a value of at least one control bit on the storage system, wherein the value of the at least one control bit is controlled by the host device in the operational power mode and the storage system in the low power mode. ### Claim 19 (depends on 18) The machine-readable medium of claim 18, wherein the low power mode is a lower-power mode than the operational power mode. ### Claim 20 (depends on 18) The machine-readable medium of claim 18, wherein the first reset has a first latency and a first power requirement, wherein the second reset has a second latency and a second power requirement, and wherein the second latency is less than the first latency and the first power requirement is lower than the second power requirement. ### Claim 21 (depends on 18) The machine-readable medium of claim 18, wherein the operational power mode is a normal power mode and the low power mode is a deep sleep mode, and wherein the first reset is a normal reset including re-initialization the control circuitry, the group of non-volatile memory cells, and wherein the second reset is a modified reset including a limited re-initialization of the storage system to decrease a time of the transition from the low power mode to the operational power mode. ### Claim 22 (depends on 18) The machine-readable medium of claim 18, wherein the storage system comprises a UFS device, wherein the at least one control bit comprises multiple control bits indicative of multiple different resets, and wherein the operations further comprise: providing, in the low power mode, one of the multiple resets in response to the hardware reset signal and the values of the multiple control bits.