Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

A processor subsystem for speculatively executing load-dependent instructions, the processor subsystem comprising:

• a memory ordering consistency queue;
• and
• a load/store unit configured to:
• detect that a memory ordering consistency queue is full for a completed load instruction;
• store data loaded by the completed load instruction into a storage location for storing data on the condition that the memory ordering consistency queue is full;
• permit instructions that are dependent on the completed load instruction to speculatively execute;
• in response to a slot becoming available in the memory ordering consistency queue, replay the completed load instruction as a replayed load instruction;
• and
• in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

A processor for speculatively executing load-dependent instructions, the processor comprising:

• a memory ordering consistency queue;
• a load/store unit configured to:
• detect that a memory ordering consistency queue is full for a completed load instruction;
• store data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full;
• permit instructions that are dependent on the completed load instruction to speculatively execute;
• in response to a slot becoming available in the memory ordering consistency queue, replay the completed load instruction as a replayed load instruction;
• and
• in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location;
• and
• one or more functional units configured to speculatively execute the instructions that are dependent on the completed load instruction.