# US 11,113,063 B2 · Method and apparatus to control the use of hierarchical branch predictors based on the effectiveness of their results > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,063 B2 - Document ID: US11113063B2 - Status: Granted - Kind: B2 - Application number: 16/565,476 - Filed: 2019-09-09 - Published: 2020-12-24 - Granted: 2021-09-07 - Earliest claimed: 2019-06-24 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: James David Dundas; Xiaoxin Fan; Shashank Nemawarkar; Madhu Saravana Sibi Govindan - Web page: https://patentgrep.com/patent/US11113063B2 ## CPC - G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer} - G06F 9/381: {Loop buffering} - G06F 9/3848: {using hybrid branch prediction, e.g. selection between prediction techniques} - H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC} - G06F 9/44: Arrangements for executing specific programs - G06F 9/46: Multiprogramming arrangements - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 2212/1021: Hit rate improvement - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter. ## Claims ### Claim 1 An apparatus comprising: a main-branch target buffer (BTB); a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction; a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB; a micro-B TB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB; and a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter; wherein both the micro-BTB confidence counter and the micro-BTB misprediction rate counter are updated in response to a commitment of a branch instruction. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the micro-BTB enablement circuit is configured compare the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter against respective threshold values. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the respective threshold value for the micro-BTB confidence counter is a value of a main-BTB confidence counter; and wherein the respective threshold value for the micro-BTB misprediction rate counter is a value of a main-BTB misprediction rate counter. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the micro-BTB enablement circuit is configured to enable a usage of the micro-BTB's prediction information if the micro-BTB confidence counter and the micro-BTB misprediction rate counter indicate that the micro-BTB is likely to be a better predictor than the main-BTB. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the apparatus includes a hashed branch predictor circuit; and wherein the micro-BTB confidence counter is configured to alter the value of the micro-BTB confidence counter based, at least in part, upon a confidence level of the hashed branch predictor circuit. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the apparatus is configured to only update the micro-BTB confidence counter and the micro-BTB misprediction rate counter during periodic sampling intervals. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the micro-BTB enablement circuit is configured to, in a first mode, enable the micro-BTB to generate prediction information, but disable the usage of the micro-BTB's prediction information; and the micro-BTB enablement circuit is configured to, in a second mode, enable the micro-BTB to generate prediction information, and the usage of the micro-BTB's prediction information. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the micro-BTB enablement circuit is configured to the usage of the micro-BTB's prediction information during period training intervals. ### Claim 9 An apparatus comprising: a main-branch target buffer (BTB); a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction; a main-BTB confidence counter configured to measure a correctness of the prediction information produced by the main-BTB; a main-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB; and a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the main-BTB confidence counter and the main-BTB misprediction rate counter; wherein both the main-BTB confidence counter and the main-BTB misprediction rate counter update in response to a commitment of a branch instruction. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the micro-BTB enablement circuit is configured compare the values of the main-BTB confidence counter and the main-BTB misprediction rate counter against respective threshold values. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the respective threshold value for the main-BTB confidence counter is a value of a micro-BTB confidence counter; and wherein the respective threshold value for the main-BTB misprediction rate counter is a value of a micro-BTB misprediction rate counter. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the micro-BTB enablement circuit is configured to enable a usage of the micro-BTB's prediction information if the main-BTB confidence counter and the main-B TB misprediction rate counter indicate that the micro-B TB is likely to be a better predictor than the main-BTB. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the apparatus includes a hashed branch predictor circuit; and wherein the main-BTB confidence counter is configured to alter the value of the main-BTB confidence counter based, at least in part, upon a confidence level of the hashed branch predictor circuit. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the apparatus is configured to only update the main-BTB confidence counter and the main-BTB misprediction rate counter during periodic sampling intervals. ### Claim 15 (depends on 9) The apparatus of claim 9, wherein the apparatus further comprises: a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB; and a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. ### Claim 16 (depends on 9) The apparatus of claim 9, wherein a plurality of predictors is associated with the micro-BTB, and wherein the micro-BTB enablement circuit is configured to enable or disable individual ones of the plurality of predictors based, at least in part, upon a sampling of the period. ### Claim 17 A system comprising: a front-end logic section configured to fetch and predict a series of instructions to be executed; and wherein the front-end logic section comprises: a main-branch target buffer (BTB); a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction; and a heuristic logic circuit comprising a plurality of counters configured to measure the effectiveness of the main-BTB and the micro-BTB, and based, at least in part, upon the plurality of counters, determine whether to enable a usage of the micro-B TB's prediction information; wherein the plurality of counters are updated, at least in part, in response to a commitment of a branch instruction. ### Claim 18 (depends on 17) The system of claim 17, wherein the heuristic logic circuit is configured to compare a prediction accuracy of the main-BTB versus the micro-BTB, and compare a moving misprediction rate of the main-BTB versus the micro-BTB.