# US 11,113,062 B2 · Inserting predefined pad values into a stream of vectors

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 11,113,062 B2
- Document ID: US11113062B2
- Status: Granted
- Kind: B2
- Application number: 16/420,480
- Filed: 2019-05-23
- Published: 2019-09-12
- Granted: 2021-09-07
- Earliest claimed: 2013-07-15
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Asheesh Bhardwaj; Timothy David Anderson; Son Hung Tran
- Web page: https://patentgrep.com/patent/US11113062B2

## CPC

- G06F 9/3016: {Decoding the operand specifier, e.g. specifier format}
- G06F 9/30014: {with variable precision}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/30047: {Prefetch instructions; cache control instructions}
- G06F 9/30098: {Register arrangements}
- G06F 9/30112: {comprising data of variable length}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/32: Address formation of the next instruction, e.g. by incrementing the instruction counter (G06F9/38 takes precedence)
- G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)}
- G06F 9/3455: {using stride}
- G06F 9/3802: {Instruction prefetching}
- G06F 9/383: {Operand prefetching (cache prefetching G06F12/0862)}
- G06F 9/3867: {using instruction pipelines}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 12/0862: with prefetch
- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811)
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 7/74: Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders {(with shifting G06F5/01)}
- G06F 9/3822: {Parallel decoding, e.g. parallel decode units}
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06F 2212/452: Instruction code
- G06F 2212/60: Details of cache memory
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Software instructions are executed on a processor within a computer system to configure a steaming engine with stream parameters to define a multidimensional array. The stream parameters define a size for each dimension of the multidimensional array and a pad value indicator. Data is fetched from a memory coupled to the streaming engine responsive to the stream parameters. A stream of vectors is formed for the multidimensional array responsive to the stream parameters from the data fetched from memory. A padded stream vector is formed that includes a specified pad value without accessing the pad value from system memory.

## Claims

### Claim 1

A method of operating a streaming engine in a computer system, the method comprising:
receiving stream parameters into control logic of the streaming engine to define a multidimensional array, wherein the stream parameters define a size for each dimension of the multidimensional array and a pad value indicator;
fetching data from a memory coupled to the streaming engine responsive to the stream parameters;
forming a stream of vectors from the data fetched from memory for the multidimensional array responsive to the stream parameters;
forming a padded stream vector for the stream of vectors that includes a pad value specified by the pad value indicator without fetching respective pad data from the memory; and
suppressing a respective access to the memory while forming the padded stream vector.

### Claim 2 (depends on 1)

The method of claim 1, in which the stream parameters define a selected dimension of the multidimensional array, and in which the padded stream vector is formed in the selected dimension of the stream of vectors.

### Claim 3 (depends on 1)

The method of claim 1, in which the pad value indicator specifies one of a minimum value, a maximum value, or zero.

### Claim 4 (depends on 1)

The method of claim 1, in which the stream parameters include an element size of the array, a number of elements to include in each vector of a stream, and a number of vectors to include in the stream for each dimension of the array.

### Claim 5 (depends on 4)

The method of claim 4, in which the pad value forms a last element of the stream of vectors.

### Claim 6 (depends on 1)

The method of claim 1, further comprising suppressing access to an address lookaside buffer while forming the padded stream vector.

### Claim 7

A system comprising:
a system memory;
a streaming engine coupled to the system memory, wherein the streaming engine comprises:
a stream template register to store stream parameters, wherein the stream parameters define a size for each dimension of a multidimensional array and a pad value indicator;
address generation logic coupled to the stream template register;
a memory interface logic coupled to receive a stream of addresses from the address generation logic and coupled to access the system memory; and
control logic coupled to the memory interface logic, wherein the control logic is configured to form a padded stream vector that includes a pad value specified by the pad value indicator without fetching respective pad data from the memory by suppressing a respective access to the system memory responsive to the stream parameters while forming the padded stream vector.

### Claim 8 (depends on 7)

The system of claim 7, further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress an access to the translation lookaside buffer by the address generation logic for forming the padded stream vector.

### Claim 9 (depends on 7)

The system of claim 7, in which all elements in the padded stream vector have a value of zero.

### Claim 10 (depends on 7)

The system of claim 7, in which an element in the padded stream vector has the pad value that is specified by the stream parameters to be one of a minimum value or a maximum value.

### Claim 11 (depends on 7)

The system of claim 7, further comprising:
a register file with outputs; and
an alignment network with inputs coupled to the outputs of the register file, the alignment network coupled to the control logic for control, the alignment network having outputs coupled to outputs of the streaming engine to provide the padded stream vector responsive to the pad value indicator.

### Claim 12 (depends on 7)

The system of claim 7 being a system on a chip (SoC), further comprising a processing unit coupled to the outputs of the streaming engine to receive a stream of vectors.

### Claim 13

A system comprising:
a system memory;
a streaming engine coupled to access the system memory, the streaming engine configured to:
receive stream parameters defining an array, wherein the stream parameters include:
a number of vectors for each dimension in the array; and
a pad value;
in response to receiving the stream parameters, generate an address stream based on the stream parameters;
for each dimension in the array:
retrieve, based on the address stream, one or more elements from the system memory; and
form the number of vectors for each dimension in the array, wherein each of the number of vectors is formed based on the one or more elements retrieved from the system memory; and
form a stream of vectors with the number of vectors for each dimension, wherein the streaming engine is operable to insert a padded vector having the pad value into the stream of vectors for each dimension; and
a processing unit coupled to outputs of the streaming engine to receive the stream of vectors for each dimension.

### Claim 14 (depends on 13)

The system of claim 13, in which the streaming engine comprises:
a stream template register to store the stream parameters; and
control logic coupled to receive the stream parameters from the stream template register.

### Claim 15 (depends on 14)

The system of claim 14, further comprising:
address generation logic configured to generate the address stream;
a memory interface logic coupled to receive the address stream from the address generation logic and coupled to access the system memory; and
wherein the control logic is operable to suppress an access to the system memory responsive to the stream parameters while forming the padded vector.

### Claim 16 (depends on 15)

The system of claim 15, further comprising a translation lookaside buffer coupled to the address generation logic, wherein the control logic is operable to suppress an access to the translation lookaside buffer by the address generation logic while forming the padded vector.

### Claim 17 (depends on 14)

The system of claim 14, further comprising:
a register file with inputs coupled to receive the one or more elements a vector fetched from the system memory; and
an alignment network with inputs coupled to outputs of the register file, the alignment network coupled to the control logic for control, the alignment network having outputs coupled to outputs of the streaming engine to provide the padded vector responsive to the stream parameters.

### Claim 18 (depends on 13)

The system of claim 13, in which all of the one or more elements in the padded vector have a value of zero.

### Claim 19 (depends on 13)

The system of claim 13, in which the pad value of the one or more elements in the padded vector is one of a minimum value and a maximum value.