# US 11,113,060 B2 · Combining states of multiple threads in a multi threaded processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,060 B2 - Document ID: US11113060B2 - Status: Granted - Kind: B2 - Application number: 16/529,122 - Filed: 2019-08-01 - Published: 2019-11-21 - Granted: 2021-09-07 - Earliest claimed: 2017-10-20 - Assignees: Graphcore Limited - Applicants: Graphcore Limited - Inventors: Simon Christian Knowles - Web page: https://patentgrep.com/patent/US11113060B2 ## CPC - G06F 9/3009: {Thread control instructions} - G06F 9/30079: {Pipeline control instructions, e.g. multicycle NOP} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/30101: {Special purpose registers} - G06F 9/30123: {according to context, e.g. thread buffers} - G06F 9/3802: {Instruction prefetching} - G06F 9/3818: {Decoding for concurrent execution} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/462: {with multiple register sets} - G06F 9/4887: {involving deadlines, e.g. rate based, periodic} - G06F 9/505: {considering the load} - G06F 9/522: {Barrier synchronisation} - G06F 15/17325: {Synchronisation; Hardware support therefor (intertask synchronisation G06F9/52)} - G06F 15/80: comprising an array of processing units with common control, e.g. single instruction multiple data processors (G06F15/82 takes precedence {; for correlation function computation G06F17/15}) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processing apparatus comprising one or more processing modules, each comprising an execution unit. The one or more processing modules are operable to run a plurality of parallel or concurrent threads, and the processing apparatus further comprises a storage location for storing an aggregated exit state of the plurality of threads. An instruction set of the processing apparatus comprises an exit instruction for inclusion in each of the plurality of threads, the exit state instruction taking an individual exit state of the respective thread as an operand. The exit instruction terminates the respective thread and also causes the individual exit state specified in the operand to contribute to the aggregated exit state. ## Claims ### Claim 1 A processing apparatus comprising: one or more processing modules each comprising a respective execution unit for executing machine code instructions, each machine code instruction being an instance of a predefined set of instruction types in an instruction set, each instruction type in the instruction set being defined by a corresponding opcode and zero or more operand fields for taking zero or more operands; wherein the one or more processing modules are operable to execute a plurality of parallel or concurrent threads; and the processing apparatus further comprises a storage location for storing an aggregated exit state of said plurality of threads; wherein the instruction set comprises an exit instruction for inclusion in each of said plurality of threads, the exit instruction taking at least an individual exit state of the respective thread as an operand; and wherein each of the one or more execution units is configured so as, in response to the opcode of the exit instruction, to terminate the respective thread, and also to cause the individual exit state specified in the operand to contribute to the aggregated exit state in said storage location. ### Claim 2 (depends on 1) The processing apparatus of claim 1, wherein the exit instruction comprises only a single operand field taking a single operand in the form of said individual exit state. ### Claim 3 (depends on 1) The processing apparatus of claim 1, wherein each of the individual exit states and the aggregated exit states is only a single bit. ### Claim 4 (depends on 3) The processing apparatus of claim 3, wherein the aggregation consists of a Boolean AND of the individual exit states, or a Boolean OR of the individual exit states. ### Claim 5 (depends on 1) The processing apparatus of claim 1, wherein the aggregated exit state comprises at least two bits representing a trinary value, indicating whether the individual binary exit states are all 1, all 0 or mixed. ### Claim 6 (depends on 1) The processing apparatus of claim 1, wherein said storage location is a dedicated exit state register. ### Claim 7 (depends on 1) The processing apparatus of claim 1, wherein the execution unit of each of the one or more processing modules comprises dedicated hardware logic configured to perform said termination and said causing of the individual exit state to contribute to the aggregated exit state. ### Claim 8 (depends on 1) The processing apparatus of claim 1, wherein each of the one or more processing modules comprises a respective pipeline comprising the respective execution unit. ### Claim 9 (depends on 1) The processing apparatus of claim 1, wherein at least one of the one or more processing modules comprises a barrel-threaded processing module, operable to run two or more of said plurality of threads concurrently by interleaving them through the respective execution unit in different respective time slots in a repeating sequence of time slots. ### Claim 10 (depends on 1) The processing apparatus of claim 1, wherein said one or more processing modules are a plurality of processing modules, operable to run two or more of said plurality of threads in parallel on the execution units of different ones of said plurality of processing modules. ### Claim 11 (depends on 9) The processing apparatus of claim 9, wherein the barrel-threaded processing module comprises a plurality of context register sets, each arranged to maintain a program state of a respective thread executing in one of the time slots. ### Claim 12 (depends on 9) The processing apparatus of claim 9, wherein said plurality of threads comprise a plurality of worker threads; and wherein the barrel-threaded processing module is further configured, in one or more of said time slots, during at least some repetitions of said sequence of time slots, to execute a supervisor thread which allocates the worker threads to the respective execution slots. ### Claim 13 (depends on 12) The processing apparatus of claim 12, wherein the plurality of context register sets comprise multiple worker context register sets, each worker context register set arranged to maintain the program state of the respective worker thread currently executing in the respective timeslot when executing the respective worker thread, and wherein the barrel-threaded processing module further comprises an additional supervisor context register set comprising additional registers arranged to store a program state of the supervisor thread. ### Claim 14 (depends on 12) The processing apparatus of claim 12, wherein the supervisor thread begins by running in each of said plurality of time slots, and then relinquishes some or all of the time slots to the respective worker threads; and wherein the exit instruction causes the supervisor thread to resume executing in the respective time slot of the worker thread that executed the exit instruction. ### Claim 15 (depends on 14) The processing apparatus of claim 14, wherein the instruction set further comprises a relinquish instruction and the respective execution unit is configured to perform said relinquishing of the respective execution slot in response to the opcode of the relinquish instruction executed by the supervisor thread in the respective time slot being relinquished. ### Claim 16 (depends on 9) The processing apparatus of claim 9, wherein the processor comprises a group of tiles each comprising an instance of the barrel-threaded processing module; and wherein the processor further comprises an interconnect for communicating between the tiles. ### Claim 17 (depends on 16) The processing apparatus of claim 16, wherein the processing apparatus is configured to automatically aggregate the aggregated exit states from the group of tiles into a global aggregate, and to make the global aggregate available to at least one thread on at least one of the processing modules. ### Claim 18 (depends on 1) The processing apparatus of claim 1, programmed to perform a machine intelligence algorithm in which each node in a graph has one or more respective input edges and one or more respective output edges with the input edges of at least some of the nodes being the output edges of at least some others of the nodes, each node comprising a respective function relating its output edges to its input edges, with each respective function being parameterized by one or more respective parameters, and each of the respective parameters having an associated error, such that the graph converges toward a solution as the errors in some or all of the parameters reduce; wherein each of at least some of the plurality of threads models a respective one of the nodes in the graph, and each of the individual exit states is used to indicate whether the errors in the one or more parameters of the respective node have satisfied a predetermined condition. ### Claim 19 A method of operating a processing apparatus comprising a plurality of processing modules, each processing module having a respective execution unit for executing machine code instructions, of an instruction set of the processing modules; wherein the method comprises: scheduling execution of a plurality of parallel or concurrent threads by the one or more processing modules; and storing an aggregated exit state of the plurality of threads; wherein the instruction set comprises an exit instruction which is included in each thread of the plurality of threads, the exit instruction taking at least an individual exit state of a respective thread as an operand; and in response to the exit instruction upon execution of a first one of the threads, triggering logic to terminate the first thread from executing, and to cause the individual exit state specified in an operand of the first thread to contribute to the aggregated exit state. ### Claim 20 (depends on 19) The method of claim 19, wherein the exit instruction comprises a single operand field taking a single operand in a form of said individual exit state. ### Claim 21 (depends on 19) The method of claim 19, wherein each of the individual exit states and the aggregated exit states is represented by a single bit. ### Claim 22 (depends on 21) The method of claim 21, wherein the aggregated exit state is represented by a Boolean AND of the individual exit states, or a Boolean OR of the individual exit states. ### Claim 23 (depends on 19) The method of claim 19, wherein the aggregated exit state comprises at least two bits representing a trinary value, indicating whether the individual binary exit states are all 1, all 0 or mixed. ### Claim 24 (depends on 19) The method of claim 19, wherein the aggregated exit state is stored in a dedicated exit state register. ### Claim 25 A processing apparatus comprising: a processing module having an execution unit configured to execute a plurality of machine code instructions in an instruction set of the processing module; wherein the processing module is further configured to execute a plurality of parallel or concurrent threads; and a storage location for storing an aggregated exit state of the plurality of threads; wherein the instruction set comprises an exit instruction for inclusion in each thread of the plurality of threads, the exit instruction taking an individual exit state of a respective thread as an operand; and wherein the execution unit is configured to, in response to a first thread including the exit instruction, terminate the first thread and also to cause an individual exit state of the first thread to contribute to the aggregated exit state in the storage location. ### Claim 26 (depends on 25) The processing apparatus of claim 25, wherein the exit instruction comprises a single operand field taking a single operand in a form of said individual exit state. ### Claim 27 (depends on 25) The processing apparatus of claim 25, further comprising: an AND gate configured to receive the individual exit state; and wherein the storage location comprises a register configured to output the aggregated exit state to an input of the AND gate and to receive an output of the AND gate. ### Claim 28 (depends on 25) The processing apparatus of claim 25, further comprising: an OR gate configured to receive the individual exit state; and wherein the storage location comprises a register configured to output the aggregated exit state to an input of the OR gate and to receive an output of the OR gate. ### Claim 29 (depends on 25) The processing apparatus of claim 25, wherein the processing module is one of a plurality of processing modules, and wherein each of the one or more processing modules comprises a respective pipeline comprising a respective execution unit. ### Claim 30 (depends on 25) The processing apparatus of claim 25, wherein the processing module is one of a plurality of processing modules, and wherein at least one of the one or more processing modules comprises a barrel-threaded processing module, operable to run two or more of the plurality of threads concurrently by interleaving the threads through a respective execution unit in different respective time slots in a repeating sequence of time slots.