# US 11,113,055 B2 · Store instruction to store instruction dependency > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 11,113,055 B2 - Document ID: US11113055B2 - Status: Granted - Kind: B2 - Application number: 16/357,380 - Filed: 2019-03-19 - Published: 2020-09-24 - Granted: 2021-09-07 - Earliest claimed: 2019-03-19 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Edward Malley; Jang-Soo Lee; Anthony Saporito; Chung-Lung K. Shum; Gregory William Alexander - Web page: https://patentgrep.com/patent/US11113055B2 ## CPC - G06F 9/30043: {LOAD or STORE instructions; Clear instruction} - G06F 9/3834: {Maintaining memory consistency} - G06F 9/30101: {Special purpose registers} - G06F 9/3838: {Dependency mechanisms, e.g. register scoreboarding} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3869: {Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A computer implemented method for marking a store instruction overlap in a processor pipeline is provided. A non-limiting example of the method includes detecting a second store instruction subsequent to a first store instruction in an instruction stream, in which there is a match between the operand address information of the first store instruction and a load instruction. The operand address information of the first store instruction is compared with the operand address information of the second store instruction to determine whether there is match. In the event of a match, the second store instruction is delayed in the processor pipeline in response to determining that there is a memory image overlap between the operand address information of the second store instruction and the first store instruction. ## Claims ### Claim 1 A computer-implemented method for creating a store instruction dependency in a processor pipeline comprising: detecting, by a processor, a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction; comparing, by the processor, the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction; and writing, by the processor, a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction; analyzing, by the processor and prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction; and delaying, by the processor, the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction, wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises: translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction, translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction. ### Claim 2 (depends on 1) The computer-implemented method of claim 1, wherein the first store instruction is stored in a dispatch store table (DST). ### Claim 3 (depends on 1) The computer-implemented method of claim 1, wherein the first store instruction is the youngest store instruction in a dispatch store table (DST). ### Claim 4 (depends on 3) The computer-implemented method of claim 3, wherein an indicator bit is stored with the first store instruction in the DST. ### Claim 5 (depends on 4) The computer-implemented method of claim 4, wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction is based on a presence of the indicator bit. ### Claim 6 (depends on 1) The computer-implemented method of claim 1, wherein delaying the second store instruction comprises dynamically inserting a number of clock cycles between issue of the second store instruction and issue of the first store instruction. ### Claim 7 A system for creating a store instruction dependency in a processor pipeline, the system comprising: a processor communicatively coupled to a memory, the processor configured to: detect a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction; compare the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction; write a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction; analyze, prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction; and delay the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction, wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises: translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction, translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction. ### Claim 8 (depends on 7) The system of claim 7, wherein the first store instruction is stored in a dispatch store table (DST). ### Claim 9 (depends on 7) The system of claim 7, wherein the first store instruction is the youngest store instruction in a dispatch store table (DST). ### Claim 10 (depends on 9) The system of claim 9, wherein the processor is further configured to store an indicator bit with the first store instruction in the DST. ### Claim 11 (depends on 10) The system of claim 10, wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction is based on a presence of the indicator bit. ### Claim 12 (depends on 7) The system of claim 7, wherein delaying the second store instruction comprises dynamically inserting a number of clock cycles between issue of the second store instruction and issue the first store instruction. ### Claim 13 A computer program product for creating a store instruction dependency in a processor pipeline, the computer product comprising a computer readable storage medium having program instructions embodied therewith, the instructions executable by a processor to cause the processor to: detect a second store instruction subsequent to a first store instruction in an instruction stream, wherein the first store instruction and the second store instruction respectively include operand address information, and wherein there is a memory image overlap in an issue queue between the operand address information of the first store instruction and operand address information of a load instruction; compare the operand address information of the first store instruction with the operand address information of the second store instruction to determine whether there is a match between the operand address information of the second store instruction and the operand address information of the first store instruction; write a scoreboard bit to a scoreboard in response to determining a match between the operand address information of the second store instruction and the operand address information of the first store instruction; analyze, prior to issuance of the second store instruction, the scoreboard to detect a determined match between the operand address information of the second store instruction and the operand address information of the first store instruction; and delay the second store instruction in the processor pipeline until a dependency is created between the second store instruction and the first store instruction, wherein comparing the operand address information of the first store instruction with the operand address information of the second store instruction comprises: translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the first store instruction, translating a vector representing a base register address, an index register address, a displacement register address to a memory image vector for the second store instruction, and comparing the memory image vector for the first store instruction to the memory image vector for the second store instruction. ### Claim 14 (depends on 13) The computer program product of claim 13, wherein the first store instruction is stored in a dispatch store table (DST). ### Claim 15 (depends on 13) The computer program product of claim 13, wherein the first store instruction is the youngest store instruction in a dispatch store table (DST). ### Claim 16 (depends on 15) The computer program product of claim 15, wherein the processor is further configured to store an indicator bit with the first store instruction in the DST. ### Claim 17 (depends on 13) The computer program product of claim 13, wherein delaying the second store instruction comprises dynamically inserting a number of clock cycles between issue of the second store instruction and the first store instruction.