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US 11,112,983 B2Granted
Recovery of memory device from a reduced power state
AssigneeMicron Technology, Inc.
InventorGiuseppe Cariello
Life of this patent
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Abstract
Devices and techniques are disclosed herein to control recovery of a memory device from a reduced power state. A memory controller can include a detection circuit configured to monitor the power supply voltage to an array of memory cells during the reduced power state. Control circuitry an initialization procedure for recovery of the memory device from the reduced power state, based on the state of the detection circuit.
Claims13
A storage system, comprising:
- a memory comprised of an array of non-volatile memory cells;
- and
- a memory controller, including,
- a voltage drop detection circuit to monitor power supply voltage to the memory during reduced power states of the storage system;
- at least one hardware register to store data that indicates a state of the power supply voltage monitored by the voltage drop detection circuit during a reduced power state relative to at least one established threshold;
- at least one additional hardware register to store data that indicates whether the shortened initialization procedure is enabled for the memory;
- and
- a processor responsive to instructions retained in the storage system, which when executed by the processor cause the processor to perform operations, comprising,
- performing an initialization procedure of the memory to recover from the reduced power state, dependent at least in part on the monitored power supply voltage to the memory during the reduced power state indicated by the data of the at least one hardware register, wherein performing the initialization procedure comprises,
- determining whether power to the memory has fallen below an established threshold voltage during a reduced power state;
- in response to determining that power to the memory has fallen below the established threshold voltage, performing a standard initialization procedure;
- in response to determining that power to the memory has not fallen below the established threshold voltage, reading data from the additional hardware register to determine whether a shortened initialization procedure is enabled;
- and
- in response to determining that a shortened initialization procedure is not enabled, performing a standard initialization procedure;
- and
- in response to determining that a shortened initialization procedure is enabled, performing a shortened initialization procedure.
13 more elements
A method of operating a storage system, the method comprising:
- monitoring a power supply voltage to a memory device of the storage system during a first reduced power state of the storage system;
- storing an indicator of a state of the monitored power supply voltage during the first reduced power state within at least one hardware register;
- storing an indicator of whether the shortened initialization procedure is enabled for the memory device in an additional hardware register;
- reading the stored indicator of the state of the monitored power supply voltage relative to a threshold;
- and
- controlling an initialization procedure of the memory device to recover from the first reduced power state based at least in part on the stored indicator of the state of the monitored power supply voltage, comprising,
- reading the stored indicator to determine whether the monitored power supply voltage fell below the threshold voltage during the first reduced power state,
- in response to determining that the monitor power supply voltage did not fall below the threshold voltage,
- reading the additional hardware register to determine whether a shortened initialization procedure is enabled for the memory device;
- upon determining that the shortened initialization procedure is not enabled for the memory device, performing a standard initialization procedure.
7 more elements
An electronic system comprising:
- a device comprising a host processor;
- a storage system connected to the device through at least a reset interface, the storage system comprising a memory comprised of an array of non-volatile memory cells;
- and
- a memory controller configured to perform an initialization procedure of the storage system subsequent to recovery of the storage system from a reduced power state, the memory controller including,
- a voltage drop detection circuit to monitor power supply voltage to the memory during the reduced power state, and to generate an indicator of the monitored voltage;
- and
- control circuitry configured to control the initialization procedure based on the monitored voltage indicator of the voltage drop detection circuit, the control circuitry comprising,
- a first hardware resister coupled to store the indicator of the monitored power supply voltage during the reduced power state;
- an additional hardware register coupled to store an indicator of whether the shortened initialization procedure is enabled for the memory;
- wherein the control circuitry is configured to perform one of a shortened initialization procedure or a standard initialization procedure, wherein the shortened initialization procedure is performed in response to the monitored voltage indicator in the first hardware register and the shortened initialization procedure enablement indicator of the additional hardware register.
7 more elements
Dependencies are inferred from the claim text.