# US 11,112,982 B2 · Power optimization for memory subsystems

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- Number: US 11,112,982 B2
- Document ID: US11112982B2
- Status: Granted
- Kind: B2
- Application number: 16/552,243
- Filed: 2019-08-27
- Published: 2021-03-04
- Granted: 2021-09-07
- Earliest claimed: 2019-08-27
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Deping He; David A. Palmer
- Web page: https://patentgrep.com/patent/US11112982B2

## CPC

- G06F 3/0632: {by initialisation or re-initialisation of storage systems}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0625: {Power saving in storage systems}
- G06F 3/0634: {by changing the state or mode of one or more devices}
- G06F 3/0653: {Monitoring storage devices or systems}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 3/0683: {Plurality of storage devices}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G06F 11/1076: {Parity data used in redundant arrays of independent storages, e.g. in RAID systems}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A processing device initializes a drive strength value of a storage device in an electronic device to a first level. The processing device detects an operation to be performed on the storage device and executes the operation. The processing device monitors a bit error rate occurring in the storage device as a result of executing the operation and determines if the bit error rate satisfies a threshold value. In response to determining that the bit error rate satisfies the threshold value, the processing device increases the drive strength value of the storage device to a second level and re-executes the operation at the increased drive strength value of the storage device.

## Claims

### Claim 1

A method comprising:
initializing a drive strength value of a memory subsystem to a first level;
executing an operation on the memory subsystem with the drive strength at the first level;
determining that a bit error rate occurring in the memory subsystem as a result of executing the operation satisfies a threshold value;
in response to determining that the bit error rate satisfies the threshold value, increasing the drive strength value of the memory subsystem to a second level;
determining an updated bit error rate based on re-executing the operation at the increased drive strength;
determining that the updated bit error rate satisfies the threshold value;
in response to determining that the updated bit error rate satisfies the threshold value, decreasing the drive strength value of the memory subsystem to the first level.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
executing a subsequent operation with the drive strength value set at the first level;
determining that a subsequent bit error rate occurring in the memory subsystem as a result of executing the subsequent operation satisfies the threshold value;
in response to determining that the subsequent bit error rate satisfies the threshold value, increasing the drive strength value of the memory subsystem to the second level;
determining, based on re-executing the subsequent operation at the increased drive strength value, that the bit error rate is within the threshold value;
maintaining the drive strength value of the memory subsystem at the second level for one or more operations following the subsequent operation; and
returning results of re-executing the subsequent operation at the increased drive strength value to a host system.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
applying an error correcting code (ECC) to correct bit errors detected in data of the re-executed operation; and
returning the corrected data to a host system.

### Claim 4 (depends on 2)

The method of claim 2, further comprising:
detecting an occurrence of a power event in a host system; and
in response to detecting the power event, re-initializing the drive strength value of the memory subsystem to the first level.

### Claim 5 (depends on 4)

The method of claim 4, wherein the power event comprises at least one of a sleep event, a power off event, or a reset event triggered by the host system.

### Claim 6 (depends on 4)

The method of claim 4, wherein the power event is a timer-based event triggered by the host system or an event that is triggered when a threshold number of operations have been executed on the memory subsystem.

### Claim 7

A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
initialize a drive strength value of a memory subsystem to a first level;
execute an operation on the memory subsystem with the drive strength at the first level;
determine that a bit error rate occurring in the memory subsystem as a result of executing the operation on the memory subsystem satisfies a threshold value;
in response to determining that the bit error rate satisfies the threshold value, increase the drive strength value of the memory subsystem to a second level;
re-execute the operation at the increased drive strength value of the memory subsystem;
determine, based on re-executing the operation at the increased drive strength value, that an updated bit error rate satisfies the threshold value; and
in response to determining that the updated bit error rate satisfies the threshold value, decrease the drive strength value of the memory subsystem to the first level.

### Claim 8 (depends on 7)

The non-transitory computer-readable storage medium of claim 7, wherein the processing device is further configured to:
execute a subsequent operation with the drive strength value at the first level;
determine that a subsequent bit error rate occurring in the memory subsystem as a result of executing the subsequent operation satisfies the threshold value;
in response to determining that the subsequent bit error rate satisfies the threshold value, increase the drive strength value of the memory subsystem to the second level;
determine, based on re-executing the subsequent operation at the increased drive strength value, that the bit error rate does not satisfy the threshold value;
maintain the drive strength value of the memory subsystem at the second level for one or more operations following the subsequent operation; and
return results of re-executing the subsequent operation at the increased drive strength value to a host system.

### Claim 9 (depends on 7)

The non-transitory computer-readable storage medium of claim 7, wherein the processing device is further configured to:
apply an error correcting code (ECC) to correct bit errors detected in data of the re-executed operation; and
return the corrected data to a host system.

### Claim 10 (depends on 8)

The non-transitory computer-readable storage medium of claim 8, wherein the processing device is further configured to:
detect an occurrence of a power event in the host system; and
in response to detecting the power event, re-initialize the drive strength value of the memory subsystem to the first level.

### Claim 11 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein the power event comprises at least one of a sleep event, a power off event, or a reset event triggered by the host system.

### Claim 12 (depends on 10)

The non-transitory computer-readable storage medium of claim 10, wherein the power event is a timer-based event triggered by the host system or an event that is triggered when a threshold number of operations have been executed on the memory subsystem.

### Claim 13

A system comprising:
a memory component; and
a processing device, operatively coupled with the memory component, to:
initialize a drive strength value of a memory subsystem to a first level;
execute an operation on the memory subsystem with the drive strength at the first level;
determine that a bit error rate occurring in the memory subsystem as a result of executing the operation satisfies a threshold value; and
in response to determining that the bit error rate satisfies the threshold value, increase the drive strength value of the memory subsystem to a second level;
re-executing the operation at the increased drive strength;
determine an updated bit error rate based on re-executing the operation at the increased drive strength;
determine that the updated bit error rate satisfies the threshold value;
in response to determining that the updated bit error rate satisfies the threshold value, decrease the drive strength value of the memory subsystem to the first level.

### Claim 14 (depends on 13)

The system of claim 13, wherein the processing device is further to:
execute a subsequent operation with the drive strength value set at the first level;
determine that a subsequent bit error rate occurring in the memory subsystem as a result of executing the subsequent operation satisfies the threshold value;
in response to determining that the subsequent bit error rate satisfies the threshold value, increase the drive strength value of the memory subsystem to the second level;
determine, based on re-executing the subsequent operation at the increased drive strength value, that the bit error rate is within the threshold value; and
maintain the drive strength value of the memory subsystem at the second level for one or more operations following the subsequent operation; and
return results of re-executing the subsequent operation at the increased drive strength value to a host system.

### Claim 15 (depends on 14)

The system of claim 14, wherein the processing device is further to:
apply an error correcting code (ECC) to correct bit errors detected in data of the re-executed operation; and
return the corrected data to a host system.

### Claim 16 (depends on 14)

The system of claim 14, wherein the processing device is further configured to:
detect an occurrence of a power event in the host system; and
in response to detecting the power event, re-initialize the drive strength value of the memory subsystem to the first level.

### Claim 17 (depends on 16)

The system of claim 16, wherein the power event comprises at least one of a sleep event, a power off event, or a reset event triggered by the host system.

### Claim 18 (depends on 16)

The system of claim 16, wherein the power event is a timer-based event triggered by the host system or an event that is triggered when a threshold number of operations have been executed on the memory subsystem.