Method and apparatus for selectable high performance or low power processor system
AssigneeSilicon Laboratories Inc.
InventorsPartha Sarathy Murali, Suryanarayana Varma Nallaparaju, Kriyangbhai Vinodbhai Shah, Venkata Rao Gunturu, Subba Reddy Kallam, Mani Kumar Kothamasu
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Abstract
A communications processor is operative in a plurality of modes including at least a high performance mode, a power savings mode with lower computational capability, and a shutdown mode with a wakeup capability. A memory for the communications processor has a high speed segment and a low speed segment, the high speed segment and low speed segment respectively on a high speed data bus and a low speed data bus, the high speed data bus and low speed data bus coupled by a bidirectional bridge.
Claims14
A processor operative for incremental operation from a power savings mode to a high performance mode, the processor comprising:
- a central processing unit (CPU);
- a performance register having a plurality of states, each state associated with a particular level of performance and power consumption;
- a processor clock source having an output coupled to the CPU and having a frequency controlled by the performance register;
- a voltage source coupled to the CPU, the voltage source controlled by the performance register, each voltage coupled to the CPU also associated with a minimum voltage required to ensure operation of the CPU at each particular clock frequency selected by the performance register;
- a high speed bus coupled to the CPU, a high speed RAM, and also to a low power RAM;
- a low power bus coupled to the CPU and also coupled to the performance register, the low power bus also coupled to a packet energy detector periodically sampling an RF energy level and storing the samples in a low power static random access memory (LPSRAM);
- a bridge coupling between the high speed bus and low power bus;
- the processor clock source comprising at least one of a ring oscillator or resistor/capacitor (RC) oscillator enabled for a low power state and a PLL enabled for a high performance state;
- the CPU periodically waking up from a power savings mode to examine the stored samples and changing the performance register to a higher performance state when an increase in RF energy level is detected.
A processor comprising:
- a central processing unit (CPU);
- a performance controller having a performance register, the performance register having a plurality of values associated with incrementally increasing performance and incrementally increasing power consumption;
- a high speed bus coupled to a low power static random access memory (LPSRAM), a high speed static random access memory (HSSRAM), and to the CPU;
- a low speed bus coupled to the CPU and the performance register, the low speed bus coupled to an RF energy detector periodically storing samples of RF energy level into the LPSRAM;
- a bridge coupling the high speed bus to the low speed bus;
- the performance controller, for each discrete value of performance register, associating a CPU voltage from a CPU voltage source, a CPU clock speed from a CPU clock source, and enabling or disabling the LPSRAM and HSSRAM;
- the CPU periodically waking up to examine the RF energy level samples in the LPSRAM and changing the performance register to a value associated with a higher performance level when the RF energy level samples indicate an increase in RF energy level.
Dependencies are inferred from the claim text.